include/configs/MPC8315ERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
   4  *
   5  * Dave Liu <daveliu@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  12 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  13 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  14 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  15 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 /*
  22  * High Level Configuration Options
  23  */
  24 #define CONFIG_E300             1 /* E300 family */
  25
  26 /*
  27  * System IO Config
  28  */
  29 #define CONFIG_SYS_SICRH                0x00000000
  30 #define CONFIG_SYS_SICRL                0x00000000 /* 3.3V, no delay */
  31
  32 #define CONFIG_HWCONFIG
  33
  34 /*
  35  * IMMR new address
  36  */
  37 #define CONFIG_SYS_IMMR         0xE0000000
  38
  39 /*
  40  * Arbiter Setup
  41  */
  42 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  43 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  44 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  45
  46 /*
  47  * DDR Setup
  48  */
  49 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  50 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  51 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  52 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  53 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  54                                 | DDRCDR_PZ_LOZ \
  55                                 | DDRCDR_NZ_LOZ \
  56                                 | DDRCDR_ODT \
  57                                 | DDRCDR_Q_DRN)
  58                                 /* 0x7b880001 */
  59 /*
  60  * Manually set up DDR parameters
  61  * consist of two chips HY5PS12621BFP-C4 from HYNIX
  62  */
  63 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  64 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  65 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  66                                 | CSCONFIG_ODT_RD_NEVER \
  67                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  68                                 | CSCONFIG_ROW_BIT_13 \
  69                                 | CSCONFIG_COL_BIT_10)
  70                                 /* 0x80010102 */
  71 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  72 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  73                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  74                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  75                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  76                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  77                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  78                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  79                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  80                                 /* 0x00220802 */
  81 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  82                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  83                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  84                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  85                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
  86                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  87                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  88                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  89                                 /* 0x27256222 */
  90 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  91                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
  92                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  93                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  94                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  95                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  96                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  97                                 /* 0x121048c5 */
  98 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
  99                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 100                                 /* 0x03600100 */
 101 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 102                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 103                                 | SDRAM_CFG_DBW_32)
 104                                 /* 0x43080000 */
 105 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 106 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 107                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 108                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 109 #define CONFIG_SYS_DDR_MODE2    0x00000000
 110
 111 /*
 112  * Memory test
 113  */
 114 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 115 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 116 #define CONFIG_SYS_MEMTEST_END          0x00140000
 117
 118 /*
 119  * The reserved memory
 120  */
 121 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 122 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 123
 124 /*
 125  * Initial RAM Base Address Setup
 126  */
 127 #define CONFIG_SYS_INIT_RAM_LOCK        1
 128 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 129 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 130 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 131                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 132
 133 /*
 134  * Local Bus Configuration & Clock Setup
 135  */
 136 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 137 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 138 #define CONFIG_SYS_LBC_LBCR             0x00040000
 139 #define CONFIG_FSL_ELBC         1
 140
 141 /*
 142  * FLASH on the Local Bus
 143  */
 144 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 145
 146 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 147 #define CONFIG_SYS_FLASH_SIZE           8       /* FLASH size is 8M */
 148
 149 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 150 /* 127 64KB sectors and 8 8KB top sectors per device */
 151 #define CONFIG_SYS_MAX_FLASH_SECT       135
 152
 153 #undef CONFIG_SYS_FLASH_CHECKSUM
 154 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 155 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 156
 157 /*
 158  * NAND Flash on the Local Bus
 159  */
 160
 161 #ifdef CONFIG_NAND_SPL
 162 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 163 #else
 164 #define CONFIG_SYS_NAND_BASE            0xE0600000
 165 #endif
 166
 167 #define CONFIG_MTD_PARTITION
 168
 169 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 170 #define CONFIG_NAND_FSL_ELBC            1
 171 #define CONFIG_SYS_NAND_BLOCK_SIZE      16384
 172 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
 173
 174 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 175 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 176 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 177 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 178 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 179
 180 /* FLASH */
 181 #define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
 182 #define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 183
 184 /* NAND */
 185 #define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V)
 186 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
 187
 188 /* Still needed for spl_minimal.c */
 189 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 190 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 191
 192 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
 193         !defined(CONFIG_NAND_SPL)
 194 #define CONFIG_SYS_RAMBOOT
 195 #else
 196 #undef CONFIG_SYS_RAMBOOT
 197 #endif
 198
 199 /*
 200  * Serial Port
 201  */
 202 #define CONFIG_SYS_NS16550_SERIAL
 203 #define CONFIG_SYS_NS16550_REG_SIZE     1
 204 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0))
 205
 206 #define CONFIG_SYS_BAUDRATE_TABLE  \
 207                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 208
 209 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 210 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 211
 212 /* I2C */
 213 #define CONFIG_SYS_I2C
 214 #define CONFIG_SYS_I2C_FSL
 215 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 216 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 217 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 218 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 219
 220 /*
 221  * Board info - revision and where boot from
 222  */
 223 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 224
 225 /*
 226  * Config on-board RTC
 227  */
 228 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 229 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 230
 231 /*
 232  * General PCI
 233  * Addresses are mapped 1-1.
 234  */
 235 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 236 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 237 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 238 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 239 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 240 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 241 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 242 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 243 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 244
 245 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 246 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 247 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 248
 249 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 250 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 251 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 252 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 253 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 254 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 255 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 256 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 257 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 258
 259 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 260 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC0000000
 261 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC0000000
 262 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 263 #define CONFIG_SYS_PCIE2_CFG_BASE       0xD0000000
 264 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x01000000
 265 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 266 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD1000000
 267 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 268
 269 #define CONFIG_PCI_INDIRECT_BRIDGE
 270 #define CONFIG_PCIE
 271
 272 #define CONFIG_EEPRO100
 273 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 274 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 275
 276 #define CONFIG_HAS_FSL_DR_USB
 277 #define CONFIG_SYS_SCCR_USBDRCM         3
 278
 279 #define CONFIG_USB_EHCI_FSL
 280 #define CONFIG_USB_PHY_TYPE     "utmi"
 281 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 282
 283 /*
 284  * TSEC
 285  */
 286 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 287 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 288 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 289 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 290
 291 /*
 292  * TSEC ethernet configuration
 293  */
 294 #define CONFIG_TSEC1            1
 295 #define CONFIG_TSEC1_NAME       "eTSEC0"
 296 #define CONFIG_TSEC2            1
 297 #define CONFIG_TSEC2_NAME       "eTSEC1"
 298 #define TSEC1_PHY_ADDR          0
 299 #define TSEC2_PHY_ADDR          1
 300 #define TSEC1_PHYIDX            0
 301 #define TSEC2_PHYIDX            0
 302 #define TSEC1_FLAGS             TSEC_GIGABIT
 303 #define TSEC2_FLAGS             TSEC_GIGABIT
 304
 305 /* Options are: eTSEC[0-1] */
 306 #define CONFIG_ETHPRIME         "eTSEC1"
 307
 308 /*
 309  * SATA
 310  */
 311 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 312 #define CONFIG_SATA1
 313 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 314 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 315 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 316 #define CONFIG_SATA2
 317 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 318 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 319 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 320
 321 #ifdef CONFIG_FSL_SATA
 322 #define CONFIG_LBA48
 323 #endif
 324
 325 /*
 326  * Environment
 327  */
 328 #if !defined(CONFIG_SYS_RAMBOOT)
 329         #define CONFIG_ENV_ADDR         \
 330                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 331         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 332         #define CONFIG_ENV_SIZE         0x2000
 333 #else
 334         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 335         #define CONFIG_ENV_SIZE         0x2000
 336 #endif
 337
 338 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 339 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 340
 341 /*
 342  * BOOTP options
 343  */
 344 #define CONFIG_BOOTP_BOOTFILESIZE
 345
 346 /*
 347  * Command line configuration.
 348  */
 349
 350 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 351
 352 /*
 353  * Miscellaneous configurable options
 354  */
 355 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 356
 357 /*
 358  * For booting Linux, the board info and command line data
 359  * have to be in the first 256 MB of memory, since this is
 360  * the maximum mapped by the Linux kernel during initialization.
 361  */
 362 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 363 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 364
 365 /*
 366  * Core HID Setup
 367  */
 368 #define CONFIG_SYS_HID0_INIT    0x000000000
 369 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 370                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 371                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 372 #define CONFIG_SYS_HID2         HID2_HBE
 373
 374 /*
 375  * MMU Setup
 376  */
 377
 378 #if defined(CONFIG_CMD_KGDB)
 379 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 380 #endif
 381
 382 /*
 383  * Environment Configuration
 384  */
 385
 386 #define CONFIG_ENV_OVERWRITE
 387
 388 #if defined(CONFIG_TSEC_ENET)
 389 #define CONFIG_HAS_ETH0
 390 #define CONFIG_HAS_ETH1
 391 #endif
 392
 393 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 394
 395 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 396         "netdev=eth0\0"                                                 \
 397         "consoledev=ttyS0\0"                                            \
 398         "ramdiskaddr=1000000\0"                                         \
 399         "ramdiskfile=ramfs.83xx\0"                                      \
 400         "fdtaddr=780000\0"                                              \
 401         "fdtfile=mpc8315erdb.dtb\0"                                     \
 402         "usb_phy_type=utmi\0"                                           \
 403         ""
 404
 405 #define CONFIG_NFSBOOTCOMMAND                                           \
 406         "setenv bootargs root=/dev/nfs rw "                             \
 407                 "nfsroot=$serverip:$rootpath "                          \
 408                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 409                                                         "$netdev:off "  \
 410                 "console=$consoledev,$baudrate $othbootargs;"           \
 411         "tftp $loadaddr $bootfile;"                                     \
 412         "tftp $fdtaddr $fdtfile;"                                       \
 413         "bootm $loadaddr - $fdtaddr"
 414
 415 #define CONFIG_RAMBOOTCOMMAND                                           \
 416         "setenv bootargs root=/dev/ram rw "                             \
 417                 "console=$consoledev,$baudrate $othbootargs;"           \
 418         "tftp $ramdiskaddr $ramdiskfile;"                               \
 419         "tftp $loadaddr $bootfile;"                                     \
 420         "tftp $fdtaddr $fdtfile;"                                       \
 421         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 422
 423 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 424
 425 #endif  /* __CONFIG_H */