include/configs/MPC8315ERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
   4  *
   5  * Dave Liu <daveliu@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  12 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  13 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  14 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  15 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 /*
  22  * High Level Configuration Options
  23  */
  24 #define CONFIG_E300             1 /* E300 family */
  25
  26 /*
  27  * System IO Config
  28  */
  29 #define CONFIG_SYS_SICRH                0x00000000
  30 #define CONFIG_SYS_SICRL                0x00000000 /* 3.3V, no delay */
  31
  32 #define CONFIG_HWCONFIG
  33
  34 /*
  35  * DDR Setup
  36  */
  37 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
  38 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  39 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  40                                 | DDRCDR_PZ_LOZ \
  41                                 | DDRCDR_NZ_LOZ \
  42                                 | DDRCDR_ODT \
  43                                 | DDRCDR_Q_DRN)
  44                                 /* 0x7b880001 */
  45 /*
  46  * Manually set up DDR parameters
  47  * consist of two chips HY5PS12621BFP-C4 from HYNIX
  48  */
  49 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  50 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  51 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  52                                 | CSCONFIG_ODT_RD_NEVER \
  53                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  54                                 | CSCONFIG_ROW_BIT_13 \
  55                                 | CSCONFIG_COL_BIT_10)
  56                                 /* 0x80010102 */
  57 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  58 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  59                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  60                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  61                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  62                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  63                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  64                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  65                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  66                                 /* 0x00220802 */
  67 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  68                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  69                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  70                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  71                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
  72                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  73                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  74                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  75                                 /* 0x27256222 */
  76 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  77                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
  78                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  79                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  80                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  81                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  82                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  83                                 /* 0x121048c5 */
  84 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
  85                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  86                                 /* 0x03600100 */
  87 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  88                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  89                                 | SDRAM_CFG_DBW_32)
  90                                 /* 0x43080000 */
  91 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
  92 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
  93                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  94                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
  95 #define CONFIG_SYS_DDR_MODE2    0x00000000
  96
  97 /*
  98  * Memory test
  99  */
 100 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 101
 102 /*
 103  * The reserved memory
 104  */
 105 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 106 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 107
 108 /*
 109  * Initial RAM Base Address Setup
 110  */
 111 #define CONFIG_SYS_INIT_RAM_LOCK        1
 112 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 113 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 114 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 115                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 116
 117 /*
 118  * FLASH on the Local Bus
 119  */
 120 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 121
 122 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 123 #define CONFIG_SYS_FLASH_SIZE           8       /* FLASH size is 8M */
 124
 125 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 126 /* 127 64KB sectors and 8 8KB top sectors per device */
 127 #define CONFIG_SYS_MAX_FLASH_SECT       135
 128
 129 #undef CONFIG_SYS_FLASH_CHECKSUM
 130 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 131 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 132
 133 /*
 134  * NAND Flash on the Local Bus
 135  */
 136
 137 #ifdef CONFIG_NAND_SPL
 138 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 139 #else
 140 #define CONFIG_SYS_NAND_BASE            0xE0600000
 141 #endif
 142
 143 #define CONFIG_MTD_PARTITION
 144
 145 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 146 #define CONFIG_NAND_FSL_ELBC            1
 147 #define CONFIG_SYS_NAND_BLOCK_SIZE      16384
 148 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
 149
 150 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 151 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 152 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 153 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 154 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 155
 156
 157
 158 /* Still needed for spl_minimal.c */
 159 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 160 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 161
 162 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
 163         !defined(CONFIG_NAND_SPL)
 164 #define CONFIG_SYS_RAMBOOT
 165 #else
 166 #undef CONFIG_SYS_RAMBOOT
 167 #endif
 168
 169 /*
 170  * Serial Port
 171  */
 172 #define CONFIG_SYS_NS16550_SERIAL
 173 #define CONFIG_SYS_NS16550_REG_SIZE     1
 174 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0))
 175
 176 #define CONFIG_SYS_BAUDRATE_TABLE  \
 177                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 178
 179 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 180 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 181
 182 /* I2C */
 183 #define CONFIG_SYS_I2C
 184 #define CONFIG_SYS_I2C_FSL
 185 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 186 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 187 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 188 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 189
 190 /*
 191  * Board info - revision and where boot from
 192  */
 193 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 194
 195 /*
 196  * Config on-board RTC
 197  */
 198 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 199 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 200
 201 /*
 202  * General PCI
 203  * Addresses are mapped 1-1.
 204  */
 205 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 206 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 207 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 208 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 209 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 210 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 211 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 212 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 213 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 214
 215 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 216 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 217 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 218
 219 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 220 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 221 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 222 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 223 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 224 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 225 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 226 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 227 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 228
 229 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 230 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC0000000
 231 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC0000000
 232 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 233 #define CONFIG_SYS_PCIE2_CFG_BASE       0xD0000000
 234 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x01000000
 235 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 236 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD1000000
 237 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 238
 239 #define CONFIG_PCI_INDIRECT_BRIDGE
 240 #define CONFIG_PCIE
 241
 242 #define CONFIG_EEPRO100
 243 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 244 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 245
 246 #define CONFIG_HAS_FSL_DR_USB
 247 #define CONFIG_SYS_SCCR_USBDRCM         3
 248
 249 #define CONFIG_USB_EHCI_FSL
 250 #define CONFIG_USB_PHY_TYPE     "utmi"
 251 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 252
 253 /*
 254  * TSEC
 255  */
 256 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 257 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 258 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 259 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 260
 261 /*
 262  * TSEC ethernet configuration
 263  */
 264 #define CONFIG_TSEC1            1
 265 #define CONFIG_TSEC1_NAME       "eTSEC0"
 266 #define CONFIG_TSEC2            1
 267 #define CONFIG_TSEC2_NAME       "eTSEC1"
 268 #define TSEC1_PHY_ADDR          0
 269 #define TSEC2_PHY_ADDR          1
 270 #define TSEC1_PHYIDX            0
 271 #define TSEC2_PHYIDX            0
 272 #define TSEC1_FLAGS             TSEC_GIGABIT
 273 #define TSEC2_FLAGS             TSEC_GIGABIT
 274
 275 /* Options are: eTSEC[0-1] */
 276 #define CONFIG_ETHPRIME         "eTSEC1"
 277
 278 /*
 279  * SATA
 280  */
 281 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 282 #define CONFIG_SATA1
 283 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 284 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 285 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 286 #define CONFIG_SATA2
 287 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 288 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 289 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 290
 291 #ifdef CONFIG_FSL_SATA
 292 #define CONFIG_LBA48
 293 #endif
 294
 295 /*
 296  * Environment
 297  */
 298
 299 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 300 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 301
 302 /*
 303  * BOOTP options
 304  */
 305 #define CONFIG_BOOTP_BOOTFILESIZE
 306
 307 /*
 308  * Command line configuration.
 309  */
 310
 311 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 312
 313 /*
 314  * Miscellaneous configurable options
 315  */
 316 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 317
 318 /*
 319  * For booting Linux, the board info and command line data
 320  * have to be in the first 256 MB of memory, since this is
 321  * the maximum mapped by the Linux kernel during initialization.
 322  */
 323 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 324 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 325
 326 /*
 327  * MMU Setup
 328  */
 329
 330 #if defined(CONFIG_CMD_KGDB)
 331 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 332 #endif
 333
 334 /*
 335  * Environment Configuration
 336  */
 337
 338 #define CONFIG_ENV_OVERWRITE
 339
 340 #if defined(CONFIG_TSEC_ENET)
 341 #define CONFIG_HAS_ETH0
 342 #define CONFIG_HAS_ETH1
 343 #endif
 344
 345 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 346
 347 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 348         "netdev=eth0\0"                                                 \
 349         "consoledev=ttyS0\0"                                            \
 350         "ramdiskaddr=1000000\0"                                         \
 351         "ramdiskfile=ramfs.83xx\0"                                      \
 352         "fdtaddr=780000\0"                                              \
 353         "fdtfile=mpc8315erdb.dtb\0"                                     \
 354         "usb_phy_type=utmi\0"                                           \
 355         ""
 356
 357 #define CONFIG_NFSBOOTCOMMAND                                           \
 358         "setenv bootargs root=/dev/nfs rw "                             \
 359                 "nfsroot=$serverip:$rootpath "                          \
 360                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 361                                                         "$netdev:off "  \
 362                 "console=$consoledev,$baudrate $othbootargs;"           \
 363         "tftp $loadaddr $bootfile;"                                     \
 364         "tftp $fdtaddr $fdtfile;"                                       \
 365         "bootm $loadaddr - $fdtaddr"
 366
 367 #define CONFIG_RAMBOOTCOMMAND                                           \
 368         "setenv bootargs root=/dev/ram rw "                             \
 369                 "console=$consoledev,$baudrate $othbootargs;"           \
 370         "tftp $ramdiskaddr $ramdiskfile;"                               \
 371         "tftp $loadaddr $bootfile;"                                     \
 372         "tftp $fdtaddr $fdtfile;"                                       \
 373         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 374
 375 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 376
 377 #endif  /* __CONFIG_H */