include/configs/MPC8313ERDB_NOR.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   4  */
   5 /*
   6  * mpc8313epb board configuration file
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 #define CONFIG_PCI_INDIRECT_BRIDGE
  22 #define CONFIG_FSL_ELBC 1
  23
  24 /*
  25  * On-board devices
  26  *
  27  * TSEC1 is VSC switch
  28  * TSEC2 is SoC TSEC
  29  */
  30 #define CONFIG_VSC7385_ENET
  31 #define CONFIG_TSEC2
  32
  33 #define CONFIG_SYS_IMMR         0xE0000000
  34
  35 #define CONFIG_SYS_MEMTEST_START        0x00001000
  36 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  37
  38 /* Early revs of this board will lock up hard when attempting
  39  * to access the PMC registers, unless a JTAG debugger is
  40  * connected, or some resistor modifications are made.
  41  */
  42 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  43
  44 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  45 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  46
  47 /*
  48  * Device configurations
  49  */
  50
  51 /* Vitesse 7385 */
  52
  53 #ifdef CONFIG_VSC7385_ENET
  54
  55 #define CONFIG_TSEC1
  56
  57 /* The flash address and size of the VSC7385 firmware image */
  58 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  59 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  60
  61 #endif
  62
  63 /*
  64  * DDR Setup
  65  */
  66 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  67 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  68 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  69
  70 /*
  71  * Manually set up DDR parameters, as this board does not
  72  * seem to have the SPD connected to I2C.
  73  */
  74 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
  75 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  76                                 | CSCONFIG_ODT_RD_NEVER \
  77                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  78                                 | CSCONFIG_ROW_BIT_13 \
  79                                 | CSCONFIG_COL_BIT_10)
  80                                 /* 0x80010102 */
  81
  82 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  83 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  84                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  85                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  86                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  87                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  88                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  89                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  90                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  91                                 /* 0x00220802 */
  92 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  93                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  94                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  95                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  96                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
  97                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
  98                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  99                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 100                                 /* 0x3835a322 */
 101 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 102                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 103                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 104                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 105                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 106                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 107                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 108                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 109 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 110                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 111                                 /* 0x05100500 */
 112 #if defined(CONFIG_DDR_2T_TIMING)
 113 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 114                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 115                                 | SDRAM_CFG_DBW_32 \
 116                                 | SDRAM_CFG_2T_EN)
 117                                 /* 0x43088000 */
 118 #else
 119 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 120                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 121                                 | SDRAM_CFG_DBW_32)
 122                                 /* 0x43080000 */
 123 #endif
 124 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 125 /* set burst length to 8 for 32-bit data path */
 126 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 127                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 128                                 /* 0x44480632 */
 129 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 130
 131 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 132                                 /*0x02000000*/
 133 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 134                                 | DDRCDR_PZ_NOMZ \
 135                                 | DDRCDR_NZ_NOMZ \
 136                                 | DDRCDR_M_ODR)
 137
 138 /*
 139  * FLASH on the Local Bus
 140  */
 141 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 142 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 143 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 144 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 145
 146 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 147 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 148
 149 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 150 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 151
 152 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 153         !defined(CONFIG_SPL_BUILD)
 154 #define CONFIG_SYS_RAMBOOT
 155 #endif
 156
 157 #define CONFIG_SYS_INIT_RAM_LOCK        1
 158 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 159 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 160
 161 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 162                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 163 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 164
 165 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 166 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 167 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 168
 169 /*
 170  * Local Bus LCRR and LBCR regs
 171  */
 172 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 173 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 174 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 175                                 | (0xFF << LBCR_BMT_SHIFT) \
 176                                 | 0xF)  /* 0x0004ff0f */
 177
 178                                 /* LB refresh timer prescal, 266MHz/32 */
 179 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
 180
 181 /* drivers/mtd/nand/nand.c */
 182 #define CONFIG_SYS_NAND_BASE            0xE2800000
 183
 184 #define CONFIG_MTD_PARTITION
 185
 186 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 187 #define CONFIG_NAND_FSL_ELBC 1
 188 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 189 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 190
 191 /* FLASH*/
 192 #define CONFIG_SYS_BR0_PRELIM   (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
 193 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 194
 195 /* NAND */
 196 #define CONFIG_SYS_BR1_PRELIM   (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V)
 197 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
 198
 199 /* Still needed for spl_minimal.c */
 200 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 201 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 202
 203 /* local bus write LED / read status buffer (BCSR) mapping */
 204 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 205 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 206                                         /* map at 0xFA000000 on LCS3 */
 207 /* BCSR */
 208 #define CONFIG_SYS_BR3_PRELIM           (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
 209 #define CONFIG_SYS_OR3_PRELIM           (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 210 /* Vitesse 7385 */
 211
 212 #ifdef CONFIG_VSC7385_ENET
 213
 214                                         /* VSC7385 Base address on LCS2 */
 215 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 216 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 217
 218 /* VSC7385 */
 219 #define CONFIG_SYS_BR2_PRELIM           (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
 220 #define CONFIG_SYS_OR2_PRELIM           (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 221
 222 #endif
 223
 224 #define CONFIG_MPC83XX_GPIO 1
 225
 226 /*
 227  * Serial Port
 228  */
 229 #define CONFIG_SYS_NS16550_SERIAL
 230 #define CONFIG_SYS_NS16550_REG_SIZE     1
 231
 232 #define CONFIG_SYS_BAUDRATE_TABLE       \
 233         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 234
 235 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 236 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 237
 238 /* I2C */
 239 #define CONFIG_SYS_I2C
 240 #define CONFIG_SYS_I2C_FSL
 241 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 242 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 243 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 244 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 245 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 246 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 247 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 248
 249 /*
 250  * General PCI
 251  * Addresses are mapped 1-1.
 252  */
 253 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 254 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 255 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 256 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 257 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 258 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 259 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 260 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 261 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 262
 263 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 264
 265 /*
 266  * TSEC
 267  */
 268
 269 #define CONFIG_GMII                     /* MII PHY management */
 270
 271 #ifdef CONFIG_TSEC1
 272 #define CONFIG_HAS_ETH0
 273 #define CONFIG_TSEC1_NAME       "TSEC0"
 274 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 275 #define TSEC1_PHY_ADDR          0x1c
 276 #define TSEC1_FLAGS             TSEC_GIGABIT
 277 #define TSEC1_PHYIDX            0
 278 #endif
 279
 280 #ifdef CONFIG_TSEC2
 281 #define CONFIG_HAS_ETH1
 282 #define CONFIG_TSEC2_NAME       "TSEC1"
 283 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 284 #define TSEC2_PHY_ADDR          4
 285 #define TSEC2_FLAGS             TSEC_GIGABIT
 286 #define TSEC2_PHYIDX            0
 287 #endif
 288
 289 /* Options are: TSEC[0-1] */
 290 #define CONFIG_ETHPRIME                 "TSEC1"
 291
 292 /*
 293  * Configure on-board RTC
 294  */
 295 #define CONFIG_RTC_DS1337
 296 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 297
 298 /*
 299  * Environment
 300  */
 301 #if !defined(CONFIG_SYS_RAMBOOT)
 302         #define CONFIG_ENV_ADDR         \
 303                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 304         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 305         #define CONFIG_ENV_SIZE         0x2000
 306
 307 /* Address and size of Redundant Environment Sector */
 308 #else
 309         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 310         #define CONFIG_ENV_SIZE         0x2000
 311 #endif
 312
 313 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 314 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 315
 316 /*
 317  * BOOTP options
 318  */
 319 #define CONFIG_BOOTP_BOOTFILESIZE
 320
 321 /*
 322  * Command line configuration.
 323  */
 324
 325 /*
 326  * Miscellaneous configurable options
 327  */
 328 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 329 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 330
 331                                 /* Boot Argument Buffer Size */
 332 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 333
 334 /*
 335  * For booting Linux, the board info and command line data
 336  * have to be in the first 256 MB of memory, since this is
 337  * the maximum mapped by the Linux kernel during initialization.
 338  */
 339                                 /* Initial Memory map for Linux*/
 340 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 341 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 342
 343 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 344
 345 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
 346
 347 /* System IO Config */
 348 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 349                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 350 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 351
 352 #define CONFIG_SYS_HID0_INIT    0x000000000
 353 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 354                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 355                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 356
 357 #define CONFIG_SYS_HID2 HID2_HBE
 358
 359 /*
 360  * Environment Configuration
 361  */
 362 #define CONFIG_ENV_OVERWRITE
 363
 364 #define CONFIG_NETDEV           "eth1"
 365
 366 #define CONFIG_HOSTNAME         "mpc8313erdb"
 367 #define CONFIG_ROOTPATH         "/nfs/root/path"
 368 #define CONFIG_BOOTFILE         "uImage"
 369                                 /* U-Boot image on TFTP server */
 370 #define CONFIG_UBOOTPATH        "u-boot.bin"
 371 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 372
 373                                 /* default location for tftp and bootm */
 374 #define CONFIG_LOADADDR         800000
 375
 376 #define CONFIG_EXTRA_ENV_SETTINGS \
 377         "netdev=" CONFIG_NETDEV "\0"                                    \
 378         "ethprime=TSEC1\0"                                              \
 379         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 380         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 381                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 382                         " +$filesize; " \
 383                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 384                         " +$filesize; " \
 385                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 386                         " $filesize; "  \
 387                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 388                         " +$filesize; " \
 389                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 390                         " $filesize\0"  \
 391         "fdtaddr=780000\0"                                              \
 392         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 393         "console=ttyS0\0"                                               \
 394         "setbootargs=setenv bootargs "                                  \
 395                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 396         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 397                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 398                                                         "$netdev:off " \
 399                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 400
 401 #define CONFIG_NFSBOOTCOMMAND                                           \
 402         "setenv rootdev /dev/nfs;"                                      \
 403         "run setbootargs;"                                              \
 404         "run setipargs;"                                                \
 405         "tftp $loadaddr $bootfile;"                                     \
 406         "tftp $fdtaddr $fdtfile;"                                       \
 407         "bootm $loadaddr - $fdtaddr"
 408
 409 #define CONFIG_RAMBOOTCOMMAND                                           \
 410         "setenv rootdev /dev/ram;"                                      \
 411         "run setbootargs;"                                              \
 412         "tftp $ramdiskaddr $ramdiskfile;"                               \
 413         "tftp $loadaddr $bootfile;"                                     \
 414         "tftp $fdtaddr $fdtfile;"                                       \
 415         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 416
 417 #endif  /* __CONFIG_H */