1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
6 * mpc8313epb board configuration file
13 * High Level Configuration Options
17 #ifndef CONFIG_SYS_MONITOR_BASE
18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
21 #define CONFIG_PCI_INDIRECT_BRIDGE
22 #define CONFIG_FSL_ELBC 1
30 #define CONFIG_VSC7385_ENET
33 #define CONFIG_SYS_MEMTEST_START 0x00001000
34 #define CONFIG_SYS_MEMTEST_END 0x07f00000
36 /* Early revs of this board will lock up hard when attempting
37 * to access the PMC registers, unless a JTAG debugger is
38 * connected, or some resistor modifications are made.
40 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
43 * Device configurations
48 #ifdef CONFIG_VSC7385_ENET
52 /* The flash address and size of the VSC7385 firmware image */
53 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
54 #define CONFIG_VSC7385_IMAGE_SIZE 8192
61 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
62 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
65 * Manually set up DDR parameters, as this board does not
66 * seem to have the SPD connected to I2C.
68 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
69 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
70 | CSCONFIG_ODT_RD_NEVER \
71 | CSCONFIG_ODT_WR_ONLY_CURRENT \
72 | CSCONFIG_ROW_BIT_13 \
73 | CSCONFIG_COL_BIT_10)
76 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
77 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
78 | (0 << TIMING_CFG0_WRT_SHIFT) \
79 | (0 << TIMING_CFG0_RRT_SHIFT) \
80 | (0 << TIMING_CFG0_WWT_SHIFT) \
81 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
82 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
83 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
84 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
86 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
87 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
88 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
89 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
90 | (10 << TIMING_CFG1_REFREC_SHIFT) \
91 | (3 << TIMING_CFG1_WRREC_SHIFT) \
92 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
93 | (2 << TIMING_CFG1_WRTORD_SHIFT))
95 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
96 | (5 << TIMING_CFG2_CPO_SHIFT) \
97 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
98 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
99 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
100 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
101 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
102 /* 0x129048c6 */ /* P9-45,may need tuning */
103 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
104 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
106 #if defined(CONFIG_DDR_2T_TIMING)
107 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
108 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
113 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
114 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
118 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
119 /* set burst length to 8 for 32-bit data path */
120 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
121 | (0x0632 << SDRAM_MODE_SD_SHIFT))
123 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
125 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
127 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
133 * FLASH on the Local Bus
135 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
136 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
137 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
138 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
140 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
141 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
143 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
144 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
146 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
147 !defined(CONFIG_SPL_BUILD)
148 #define CONFIG_SYS_RAMBOOT
151 #define CONFIG_SYS_INIT_RAM_LOCK 1
152 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
153 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
155 #define CONFIG_SYS_GBL_DATA_OFFSET \
156 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
157 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
159 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
160 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
161 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
164 * Local Bus LCRR and LBCR regs
166 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
167 | (0xFF << LBCR_BMT_SHIFT) \
168 | 0xF) /* 0x0004ff0f */
170 /* LB refresh timer prescal, 266MHz/32 */
171 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
173 /* drivers/mtd/nand/nand.c */
174 #define CONFIG_SYS_NAND_BASE 0xE2800000
176 #define CONFIG_MTD_PARTITION
178 #define CONFIG_SYS_MAX_NAND_DEVICE 1
179 #define CONFIG_NAND_FSL_ELBC 1
180 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
181 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
183 /* Still needed for spl_minimal.c */
184 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
185 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
187 /* local bus write LED / read status buffer (BCSR) mapping */
188 #define CONFIG_SYS_BCSR_ADDR 0xFA000000
189 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
190 /* map at 0xFA000000 on LCS3 */
193 #ifdef CONFIG_VSC7385_ENET
195 /* VSC7385 Base address on LCS2 */
196 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
197 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
202 #define CONFIG_MPC83XX_GPIO 1
207 #define CONFIG_SYS_NS16550_SERIAL
208 #define CONFIG_SYS_NS16550_REG_SIZE 1
210 #define CONFIG_SYS_BAUDRATE_TABLE \
211 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
213 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
214 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
217 #define CONFIG_SYS_I2C
218 #define CONFIG_SYS_I2C_FSL
219 #define CONFIG_SYS_FSL_I2C_SPEED 400000
220 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
221 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
222 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
223 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
224 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
225 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
229 * Addresses are mapped 1-1.
231 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
232 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
233 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
234 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
235 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
236 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
237 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
238 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
239 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
241 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
247 #define CONFIG_GMII /* MII PHY management */
250 #define CONFIG_HAS_ETH0
251 #define CONFIG_TSEC1_NAME "TSEC0"
252 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
253 #define TSEC1_PHY_ADDR 0x1c
254 #define TSEC1_FLAGS TSEC_GIGABIT
255 #define TSEC1_PHYIDX 0
259 #define CONFIG_HAS_ETH1
260 #define CONFIG_TSEC2_NAME "TSEC1"
261 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
262 #define TSEC2_PHY_ADDR 4
263 #define TSEC2_FLAGS TSEC_GIGABIT
264 #define TSEC2_PHYIDX 0
267 /* Options are: TSEC[0-1] */
268 #define CONFIG_ETHPRIME "TSEC1"
271 * Configure on-board RTC
273 #define CONFIG_RTC_DS1337
274 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
279 #if !defined(CONFIG_SYS_RAMBOOT)
280 #define CONFIG_ENV_ADDR \
281 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
282 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
283 #define CONFIG_ENV_SIZE 0x2000
285 /* Address and size of Redundant Environment Sector */
287 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
288 #define CONFIG_ENV_SIZE 0x2000
291 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
292 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
297 #define CONFIG_BOOTP_BOOTFILESIZE
300 * Command line configuration.
304 * Miscellaneous configurable options
306 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
307 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
309 /* Boot Argument Buffer Size */
310 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
313 * For booting Linux, the board info and command line data
314 * have to be in the first 256 MB of memory, since this is
315 * the maximum mapped by the Linux kernel during initialization.
317 /* Initial Memory map for Linux*/
318 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
319 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
321 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
323 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
325 /* System IO Config */
326 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
327 /* Enable Internal USB Phy and GPIO on LCD Connector */
328 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
331 * Environment Configuration
333 #define CONFIG_ENV_OVERWRITE
335 #define CONFIG_NETDEV "eth1"
337 #define CONFIG_HOSTNAME "mpc8313erdb"
338 #define CONFIG_ROOTPATH "/nfs/root/path"
339 #define CONFIG_BOOTFILE "uImage"
340 /* U-Boot image on TFTP server */
341 #define CONFIG_UBOOTPATH "u-boot.bin"
342 #define CONFIG_FDTFILE "mpc8313erdb.dtb"
344 /* default location for tftp and bootm */
345 #define CONFIG_LOADADDR 800000
347 #define CONFIG_EXTRA_ENV_SETTINGS \
348 "netdev=" CONFIG_NETDEV "\0" \
350 "uboot=" CONFIG_UBOOTPATH "\0" \
351 "tftpflash=tftpboot $loadaddr $uboot; " \
352 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
354 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
356 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
358 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
360 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
363 "fdtfile=" CONFIG_FDTFILE "\0" \
365 "setbootargs=setenv bootargs " \
366 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
367 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
368 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
370 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
372 #define CONFIG_NFSBOOTCOMMAND \
373 "setenv rootdev /dev/nfs;" \
376 "tftp $loadaddr $bootfile;" \
377 "tftp $fdtaddr $fdtfile;" \
378 "bootm $loadaddr - $fdtaddr"
380 #define CONFIG_RAMBOOTCOMMAND \
381 "setenv rootdev /dev/ram;" \
383 "tftp $ramdiskaddr $ramdiskfile;" \
384 "tftp $loadaddr $bootfile;" \
385 "tftp $fdtaddr $fdtfile;" \
386 "bootm $loadaddr $ramdiskaddr $fdtaddr"
388 #endif /* __CONFIG_H */