include/configs/MPC8313ERDB_NOR.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   4  */
   5 /*
   6  * mpc8313epb board configuration file
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 #define CONFIG_PCI_INDIRECT_BRIDGE
  22 #define CONFIG_FSL_ELBC 1
  23
  24 /*
  25  * On-board devices
  26  *
  27  * TSEC1 is VSC switch
  28  * TSEC2 is SoC TSEC
  29  */
  30 #define CONFIG_VSC7385_ENET
  31 #define CONFIG_TSEC2
  32
  33 #define CONFIG_SYS_MEMTEST_START        0x00001000
  34 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  35
  36 /* Early revs of this board will lock up hard when attempting
  37  * to access the PMC registers, unless a JTAG debugger is
  38  * connected, or some resistor modifications are made.
  39  */
  40 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  41
  42 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  43 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  44
  45 /*
  46  * Device configurations
  47  */
  48
  49 /* Vitesse 7385 */
  50
  51 #ifdef CONFIG_VSC7385_ENET
  52
  53 #define CONFIG_TSEC1
  54
  55 /* The flash address and size of the VSC7385 firmware image */
  56 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  57 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  58
  59 #endif
  60
  61 /*
  62  * DDR Setup
  63  */
  64 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  65 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  66 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  67
  68 /*
  69  * Manually set up DDR parameters, as this board does not
  70  * seem to have the SPD connected to I2C.
  71  */
  72 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
  73 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  74                                 | CSCONFIG_ODT_RD_NEVER \
  75                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  76                                 | CSCONFIG_ROW_BIT_13 \
  77                                 | CSCONFIG_COL_BIT_10)
  78                                 /* 0x80010102 */
  79
  80 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  81 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  82                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  83                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  84                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  85                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  86                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  87                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  88                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  89                                 /* 0x00220802 */
  90 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  91                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  92                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  93                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  94                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
  95                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
  96                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  97                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  98                                 /* 0x3835a322 */
  99 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 100                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 101                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 102                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 103                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 104                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 105                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 106                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 107 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 108                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 109                                 /* 0x05100500 */
 110 #if defined(CONFIG_DDR_2T_TIMING)
 111 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 112                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 113                                 | SDRAM_CFG_DBW_32 \
 114                                 | SDRAM_CFG_2T_EN)
 115                                 /* 0x43088000 */
 116 #else
 117 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 118                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 119                                 | SDRAM_CFG_DBW_32)
 120                                 /* 0x43080000 */
 121 #endif
 122 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 123 /* set burst length to 8 for 32-bit data path */
 124 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 125                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 126                                 /* 0x44480632 */
 127 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 128
 129 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 130                                 /*0x02000000*/
 131 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 132                                 | DDRCDR_PZ_NOMZ \
 133                                 | DDRCDR_NZ_NOMZ \
 134                                 | DDRCDR_M_ODR)
 135
 136 /*
 137  * FLASH on the Local Bus
 138  */
 139 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 140 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 141 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 142 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 143
 144 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 145 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 146
 147 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 148 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 149
 150 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 151         !defined(CONFIG_SPL_BUILD)
 152 #define CONFIG_SYS_RAMBOOT
 153 #endif
 154
 155 #define CONFIG_SYS_INIT_RAM_LOCK        1
 156 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 157 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 158
 159 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 160                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 161 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 162
 163 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 164 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 165 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 166
 167 /*
 168  * Local Bus LCRR and LBCR regs
 169  */
 170 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 171 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 172 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 173                                 | (0xFF << LBCR_BMT_SHIFT) \
 174                                 | 0xF)  /* 0x0004ff0f */
 175
 176                                 /* LB refresh timer prescal, 266MHz/32 */
 177 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
 178
 179 /* drivers/mtd/nand/nand.c */
 180 #define CONFIG_SYS_NAND_BASE            0xE2800000
 181
 182 #define CONFIG_MTD_PARTITION
 183
 184 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 185 #define CONFIG_NAND_FSL_ELBC 1
 186 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 187 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 188
 189 /* Still needed for spl_minimal.c */
 190 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 191 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 192
 193 /* local bus write LED / read status buffer (BCSR) mapping */
 194 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 195 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 196                                         /* map at 0xFA000000 on LCS3 */
 197 /* Vitesse 7385 */
 198
 199 #ifdef CONFIG_VSC7385_ENET
 200
 201                                         /* VSC7385 Base address on LCS2 */
 202 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 203 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 204
 205
 206 #endif
 207
 208 #define CONFIG_MPC83XX_GPIO 1
 209
 210 /*
 211  * Serial Port
 212  */
 213 #define CONFIG_SYS_NS16550_SERIAL
 214 #define CONFIG_SYS_NS16550_REG_SIZE     1
 215
 216 #define CONFIG_SYS_BAUDRATE_TABLE       \
 217         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 218
 219 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 220 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 221
 222 /* I2C */
 223 #define CONFIG_SYS_I2C
 224 #define CONFIG_SYS_I2C_FSL
 225 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 226 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 227 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 228 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 229 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 230 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 231 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 232
 233 /*
 234  * General PCI
 235  * Addresses are mapped 1-1.
 236  */
 237 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 238 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 239 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 240 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 241 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 242 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 243 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 244 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 245 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 246
 247 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 248
 249 /*
 250  * TSEC
 251  */
 252
 253 #define CONFIG_GMII                     /* MII PHY management */
 254
 255 #ifdef CONFIG_TSEC1
 256 #define CONFIG_HAS_ETH0
 257 #define CONFIG_TSEC1_NAME       "TSEC0"
 258 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 259 #define TSEC1_PHY_ADDR          0x1c
 260 #define TSEC1_FLAGS             TSEC_GIGABIT
 261 #define TSEC1_PHYIDX            0
 262 #endif
 263
 264 #ifdef CONFIG_TSEC2
 265 #define CONFIG_HAS_ETH1
 266 #define CONFIG_TSEC2_NAME       "TSEC1"
 267 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 268 #define TSEC2_PHY_ADDR          4
 269 #define TSEC2_FLAGS             TSEC_GIGABIT
 270 #define TSEC2_PHYIDX            0
 271 #endif
 272
 273 /* Options are: TSEC[0-1] */
 274 #define CONFIG_ETHPRIME                 "TSEC1"
 275
 276 /*
 277  * Configure on-board RTC
 278  */
 279 #define CONFIG_RTC_DS1337
 280 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 281
 282 /*
 283  * Environment
 284  */
 285 #if !defined(CONFIG_SYS_RAMBOOT)
 286         #define CONFIG_ENV_ADDR         \
 287                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 288         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 289         #define CONFIG_ENV_SIZE         0x2000
 290
 291 /* Address and size of Redundant Environment Sector */
 292 #else
 293         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 294         #define CONFIG_ENV_SIZE         0x2000
 295 #endif
 296
 297 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 298 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 299
 300 /*
 301  * BOOTP options
 302  */
 303 #define CONFIG_BOOTP_BOOTFILESIZE
 304
 305 /*
 306  * Command line configuration.
 307  */
 308
 309 /*
 310  * Miscellaneous configurable options
 311  */
 312 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 313 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 314
 315                                 /* Boot Argument Buffer Size */
 316 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 317
 318 /*
 319  * For booting Linux, the board info and command line data
 320  * have to be in the first 256 MB of memory, since this is
 321  * the maximum mapped by the Linux kernel during initialization.
 322  */
 323                                 /* Initial Memory map for Linux*/
 324 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 325 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 326
 327 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 328
 329 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
 330
 331 /* System IO Config */
 332 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 333                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 334 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 335
 336 /*
 337  * Environment Configuration
 338  */
 339 #define CONFIG_ENV_OVERWRITE
 340
 341 #define CONFIG_NETDEV           "eth1"
 342
 343 #define CONFIG_HOSTNAME         "mpc8313erdb"
 344 #define CONFIG_ROOTPATH         "/nfs/root/path"
 345 #define CONFIG_BOOTFILE         "uImage"
 346                                 /* U-Boot image on TFTP server */
 347 #define CONFIG_UBOOTPATH        "u-boot.bin"
 348 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 349
 350                                 /* default location for tftp and bootm */
 351 #define CONFIG_LOADADDR         800000
 352
 353 #define CONFIG_EXTRA_ENV_SETTINGS \
 354         "netdev=" CONFIG_NETDEV "\0"                                    \
 355         "ethprime=TSEC1\0"                                              \
 356         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 357         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 358                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 359                         " +$filesize; " \
 360                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 361                         " +$filesize; " \
 362                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 363                         " $filesize; "  \
 364                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 365                         " +$filesize; " \
 366                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 367                         " $filesize\0"  \
 368         "fdtaddr=780000\0"                                              \
 369         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 370         "console=ttyS0\0"                                               \
 371         "setbootargs=setenv bootargs "                                  \
 372                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 373         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 374                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 375                                                         "$netdev:off " \
 376                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 377
 378 #define CONFIG_NFSBOOTCOMMAND                                           \
 379         "setenv rootdev /dev/nfs;"                                      \
 380         "run setbootargs;"                                              \
 381         "run setipargs;"                                                \
 382         "tftp $loadaddr $bootfile;"                                     \
 383         "tftp $fdtaddr $fdtfile;"                                       \
 384         "bootm $loadaddr - $fdtaddr"
 385
 386 #define CONFIG_RAMBOOTCOMMAND                                           \
 387         "setenv rootdev /dev/ram;"                                      \
 388         "run setbootargs;"                                              \
 389         "tftp $ramdiskaddr $ramdiskfile;"                               \
 390         "tftp $loadaddr $bootfile;"                                     \
 391         "tftp $fdtaddr $fdtfile;"                                       \
 392         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 393
 394 #endif  /* __CONFIG_H */