1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
6 * mpc8313epb board configuration file
13 * High Level Configuration Options
17 #ifndef CONFIG_SYS_MONITOR_BASE
18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
21 #define CONFIG_PCI_INDIRECT_BRIDGE
22 #define CONFIG_FSL_ELBC 1
30 #define CONFIG_VSC7385_ENET
33 #ifdef CONFIG_SYS_66MHZ
34 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
35 #elif defined(CONFIG_SYS_33MHZ)
36 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
38 #error Unknown oscillator frequency.
41 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
43 #define CONFIG_SYS_IMMR 0xE0000000
45 #define CONFIG_SYS_MEMTEST_START 0x00001000
46 #define CONFIG_SYS_MEMTEST_END 0x07f00000
48 /* Early revs of this board will lock up hard when attempting
49 * to access the PMC registers, unless a JTAG debugger is
50 * connected, or some resistor modifications are made.
52 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
54 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
55 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
58 * Device configurations
63 #ifdef CONFIG_VSC7385_ENET
67 /* The flash address and size of the VSC7385 firmware image */
68 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
69 #define CONFIG_VSC7385_IMAGE_SIZE 8192
76 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
77 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
78 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
81 * Manually set up DDR parameters, as this board does not
82 * seem to have the SPD connected to I2C.
84 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
85 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
86 | CSCONFIG_ODT_RD_NEVER \
87 | CSCONFIG_ODT_WR_ONLY_CURRENT \
88 | CSCONFIG_ROW_BIT_13 \
89 | CSCONFIG_COL_BIT_10)
92 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
93 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
94 | (0 << TIMING_CFG0_WRT_SHIFT) \
95 | (0 << TIMING_CFG0_RRT_SHIFT) \
96 | (0 << TIMING_CFG0_WWT_SHIFT) \
97 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
98 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
99 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
100 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
102 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
103 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
104 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
105 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
106 | (10 << TIMING_CFG1_REFREC_SHIFT) \
107 | (3 << TIMING_CFG1_WRREC_SHIFT) \
108 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
109 | (2 << TIMING_CFG1_WRTORD_SHIFT))
111 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
112 | (5 << TIMING_CFG2_CPO_SHIFT) \
113 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
114 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
115 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
116 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
117 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
118 /* 0x129048c6 */ /* P9-45,may need tuning */
119 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
120 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
122 #if defined(CONFIG_DDR_2T_TIMING)
123 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
124 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
129 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
130 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
134 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
135 /* set burst length to 8 for 32-bit data path */
136 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
137 | (0x0632 << SDRAM_MODE_SD_SHIFT))
139 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
141 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
143 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
149 * FLASH on the Local Bus
151 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
152 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
153 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
154 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
156 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
157 | BR_PS_16 /* 16 bit port */ \
158 | BR_MS_GPCM /* MSEL = GPCM */ \
160 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
165 /* 0xFF006FF7 TODO SLOW 16 MB flash size */
166 /* window base at flash base */
167 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
168 /* 16 MB window size */
169 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
171 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
172 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
174 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
175 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
177 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
178 !defined(CONFIG_SPL_BUILD)
179 #define CONFIG_SYS_RAMBOOT
182 #define CONFIG_SYS_INIT_RAM_LOCK 1
183 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
184 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
186 #define CONFIG_SYS_GBL_DATA_OFFSET \
187 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
188 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
190 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
191 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
192 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
195 * Local Bus LCRR and LBCR regs
197 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
198 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
199 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
200 | (0xFF << LBCR_BMT_SHIFT) \
201 | 0xF) /* 0x0004ff0f */
203 /* LB refresh timer prescal, 266MHz/32 */
204 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
206 /* drivers/mtd/nand/nand.c */
207 #define CONFIG_SYS_NAND_BASE 0xE2800000
209 #define CONFIG_MTD_PARTITION
211 #define CONFIG_SYS_MAX_NAND_DEVICE 1
212 #define CONFIG_NAND_FSL_ELBC 1
213 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
214 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
216 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
217 | BR_DECC_CHK_GEN /* Use HW ECC */ \
218 | BR_PS_8 /* 8 bit port */ \
219 | BR_MS_FCM /* MSEL = FCM */ \
221 #define CONFIG_SYS_OR1_PRELIM \
222 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
231 /* Still needed for spl_minimal.c */
232 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
233 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
235 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
236 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
238 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
239 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
241 /* local bus write LED / read status buffer (BCSR) mapping */
242 #define CONFIG_SYS_BCSR_ADDR 0xFA000000
243 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
244 /* map at 0xFA000000 on LCS3 */
245 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
246 | BR_PS_8 /* 8 bit port */ \
247 | BR_MS_GPCM /* MSEL = GPCM */ \
250 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
259 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
260 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
264 #ifdef CONFIG_VSC7385_ENET
266 /* VSC7385 Base address on LCS2 */
267 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
268 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
270 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
271 | BR_PS_8 /* 8 bit port */ \
272 | BR_MS_GPCM /* MSEL = GPCM */ \
274 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
284 /* Access window base at VSC7385 base */
285 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
286 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
290 #define CONFIG_MPC83XX_GPIO 1
295 #define CONFIG_SYS_NS16550_SERIAL
296 #define CONFIG_SYS_NS16550_REG_SIZE 1
298 #define CONFIG_SYS_BAUDRATE_TABLE \
299 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
301 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
302 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
305 #define CONFIG_SYS_I2C
306 #define CONFIG_SYS_I2C_FSL
307 #define CONFIG_SYS_FSL_I2C_SPEED 400000
308 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
309 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
310 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
311 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
312 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
313 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
317 * Addresses are mapped 1-1.
319 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
320 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
321 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
322 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
323 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
324 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
325 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
326 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
327 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
329 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
335 #define CONFIG_GMII /* MII PHY management */
338 #define CONFIG_HAS_ETH0
339 #define CONFIG_TSEC1_NAME "TSEC0"
340 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
341 #define TSEC1_PHY_ADDR 0x1c
342 #define TSEC1_FLAGS TSEC_GIGABIT
343 #define TSEC1_PHYIDX 0
347 #define CONFIG_HAS_ETH1
348 #define CONFIG_TSEC2_NAME "TSEC1"
349 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
350 #define TSEC2_PHY_ADDR 4
351 #define TSEC2_FLAGS TSEC_GIGABIT
352 #define TSEC2_PHYIDX 0
355 /* Options are: TSEC[0-1] */
356 #define CONFIG_ETHPRIME "TSEC1"
359 * Configure on-board RTC
361 #define CONFIG_RTC_DS1337
362 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
367 #if !defined(CONFIG_SYS_RAMBOOT)
368 #define CONFIG_ENV_ADDR \
369 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
370 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
371 #define CONFIG_ENV_SIZE 0x2000
373 /* Address and size of Redundant Environment Sector */
375 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
376 #define CONFIG_ENV_SIZE 0x2000
379 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
380 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
385 #define CONFIG_BOOTP_BOOTFILESIZE
388 * Command line configuration.
392 * Miscellaneous configurable options
394 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
395 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
397 /* Boot Argument Buffer Size */
398 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
401 * For booting Linux, the board info and command line data
402 * have to be in the first 256 MB of memory, since this is
403 * the maximum mapped by the Linux kernel during initialization.
405 /* Initial Memory map for Linux*/
406 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
407 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
409 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
411 #ifdef CONFIG_SYS_66MHZ
413 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
415 #define CONFIG_SYS_HRCW_LOW (\
416 0x20000000 /* reserved, must be set */ |\
418 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
419 HRCWL_DDR_TO_SCB_CLK_2X1 |\
420 HRCWL_CSB_TO_CLKIN_2X1 |\
421 HRCWL_CORE_TO_CSB_2X1)
423 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
425 #elif defined(CONFIG_SYS_33MHZ)
427 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
429 #define CONFIG_SYS_HRCW_LOW (\
430 0x20000000 /* reserved, must be set */ |\
432 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
433 HRCWL_DDR_TO_SCB_CLK_2X1 |\
434 HRCWL_CSB_TO_CLKIN_5X1 |\
435 HRCWL_CORE_TO_CSB_2X1)
437 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
441 #define CONFIG_SYS_HRCW_HIGH_BASE (\
443 HRCWH_PCI1_ARBITER_ENABLE |\
445 HRCWH_BOOTSEQ_DISABLE |\
446 HRCWH_SW_WATCHDOG_DISABLE |\
447 HRCWH_TSEC1M_IN_RGMII |\
448 HRCWH_TSEC2M_IN_RGMII |\
451 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
452 HRCWH_FROM_0X00000100 |\
453 HRCWH_ROM_LOC_LOCAL_16BIT |\
456 /* System IO Config */
457 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
458 /* Enable Internal USB Phy and GPIO on LCD Connector */
459 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
461 #define CONFIG_SYS_HID0_INIT 0x000000000
462 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
463 HID0_ENABLE_INSTRUCTION_CACHE | \
464 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
466 #define CONFIG_SYS_HID2 HID2_HBE
468 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
470 /* DDR @ 0x00000000 */
471 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
472 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
477 /* PCI @ 0x80000000 */
478 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
479 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
483 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
485 | BATL_CACHEINHIBIT \
486 | BATL_GUARDEDSTORAGE)
487 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
492 /* PCI2 not supported on 8313 */
493 #define CONFIG_SYS_IBAT3L (0)
494 #define CONFIG_SYS_IBAT3U (0)
495 #define CONFIG_SYS_IBAT4L (0)
496 #define CONFIG_SYS_IBAT4U (0)
498 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
499 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
501 | BATL_CACHEINHIBIT \
502 | BATL_GUARDEDSTORAGE)
503 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
508 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
509 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
510 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
512 #define CONFIG_SYS_IBAT7L (0)
513 #define CONFIG_SYS_IBAT7U (0)
515 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
516 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
517 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
518 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
519 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
520 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
521 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
522 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
523 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
524 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
525 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
526 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
527 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
528 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
529 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
530 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
533 * Environment Configuration
535 #define CONFIG_ENV_OVERWRITE
537 #define CONFIG_NETDEV "eth1"
539 #define CONFIG_HOSTNAME "mpc8313erdb"
540 #define CONFIG_ROOTPATH "/nfs/root/path"
541 #define CONFIG_BOOTFILE "uImage"
542 /* U-Boot image on TFTP server */
543 #define CONFIG_UBOOTPATH "u-boot.bin"
544 #define CONFIG_FDTFILE "mpc8313erdb.dtb"
546 /* default location for tftp and bootm */
547 #define CONFIG_LOADADDR 800000
549 #define CONFIG_EXTRA_ENV_SETTINGS \
550 "netdev=" CONFIG_NETDEV "\0" \
552 "uboot=" CONFIG_UBOOTPATH "\0" \
553 "tftpflash=tftpboot $loadaddr $uboot; " \
554 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
556 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
558 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
560 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
562 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
565 "fdtfile=" CONFIG_FDTFILE "\0" \
567 "setbootargs=setenv bootargs " \
568 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
569 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
570 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
572 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
574 #define CONFIG_NFSBOOTCOMMAND \
575 "setenv rootdev /dev/nfs;" \
578 "tftp $loadaddr $bootfile;" \
579 "tftp $fdtaddr $fdtfile;" \
580 "bootm $loadaddr - $fdtaddr"
582 #define CONFIG_RAMBOOTCOMMAND \
583 "setenv rootdev /dev/ram;" \
585 "tftp $ramdiskaddr $ramdiskfile;" \
586 "tftp $loadaddr $bootfile;" \
587 "tftp $fdtaddr $fdtfile;" \
588 "bootm $loadaddr $ramdiskaddr $fdtaddr"
590 #endif /* __CONFIG_H */