include/configs/MPC8313ERDB_NOR.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   4  */
   5 /*
   6  * mpc8313epb board configuration file
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1
  16 #define CONFIG_MPC8313ERDB      1
  17
  18 #ifndef CONFIG_SYS_MONITOR_BASE
  19 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  20 #endif
  21
  22 #define CONFIG_PCI_INDIRECT_BRIDGE
  23 #define CONFIG_FSL_ELBC 1
  24
  25 /*
  26  * On-board devices
  27  *
  28  * TSEC1 is VSC switch
  29  * TSEC2 is SoC TSEC
  30  */
  31 #define CONFIG_VSC7385_ENET
  32 #define CONFIG_TSEC2
  33
  34 #ifdef CONFIG_SYS_66MHZ
  35 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  36 #elif defined(CONFIG_SYS_33MHZ)
  37 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
  38 #else
  39 #error Unknown oscillator frequency.
  40 #endif
  41
  42 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  43
  44 #define CONFIG_SYS_IMMR         0xE0000000
  45
  46 #define CONFIG_SYS_MEMTEST_START        0x00001000
  47 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  48
  49 /* Early revs of this board will lock up hard when attempting
  50  * to access the PMC registers, unless a JTAG debugger is
  51  * connected, or some resistor modifications are made.
  52  */
  53 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  54
  55 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  56 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  57
  58 /*
  59  * Device configurations
  60  */
  61
  62 /* Vitesse 7385 */
  63
  64 #ifdef CONFIG_VSC7385_ENET
  65
  66 #define CONFIG_TSEC1
  67
  68 /* The flash address and size of the VSC7385 firmware image */
  69 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  70 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  71
  72 #endif
  73
  74 /*
  75  * DDR Setup
  76  */
  77 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  78 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  79 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  80
  81 /*
  82  * Manually set up DDR parameters, as this board does not
  83  * seem to have the SPD connected to I2C.
  84  */
  85 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
  86 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  87                                 | CSCONFIG_ODT_RD_NEVER \
  88                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  89                                 | CSCONFIG_ROW_BIT_13 \
  90                                 | CSCONFIG_COL_BIT_10)
  91                                 /* 0x80010102 */
  92
  93 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  94 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  95                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  96                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  97                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  98                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  99                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 100                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 101                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 102                                 /* 0x00220802 */
 103 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 104                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 105                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 106                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 107                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
 108                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 109                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 110                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 111                                 /* 0x3835a322 */
 112 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 113                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 114                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 115                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 116                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 117                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 118                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 119                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 120 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 121                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 122                                 /* 0x05100500 */
 123 #if defined(CONFIG_DDR_2T_TIMING)
 124 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 125                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 126                                 | SDRAM_CFG_DBW_32 \
 127                                 | SDRAM_CFG_2T_EN)
 128                                 /* 0x43088000 */
 129 #else
 130 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 131                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 132                                 | SDRAM_CFG_DBW_32)
 133                                 /* 0x43080000 */
 134 #endif
 135 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 136 /* set burst length to 8 for 32-bit data path */
 137 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 138                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 139                                 /* 0x44480632 */
 140 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 141
 142 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 143                                 /*0x02000000*/
 144 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 145                                 | DDRCDR_PZ_NOMZ \
 146                                 | DDRCDR_NZ_NOMZ \
 147                                 | DDRCDR_M_ODR)
 148
 149 /*
 150  * FLASH on the Local Bus
 151  */
 152 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 153 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 154 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 155 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 156
 157 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 158                                         | BR_PS_16      /* 16 bit port */ \
 159                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 160                                         | BR_V)         /* valid */
 161 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 162                                 | OR_GPCM_XACS \
 163                                 | OR_GPCM_SCY_9 \
 164                                 | OR_GPCM_EHTR \
 165                                 | OR_GPCM_EAD)
 166                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
 167                                         /* window base at flash base */
 168 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 169                                         /* 16 MB window size */
 170 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 171
 172 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 173 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 174
 175 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 176 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 177
 178 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 179         !defined(CONFIG_SPL_BUILD)
 180 #define CONFIG_SYS_RAMBOOT
 181 #endif
 182
 183 #define CONFIG_SYS_INIT_RAM_LOCK        1
 184 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 185 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 186
 187 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 188                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 189 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 190
 191 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 192 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 193 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 194
 195 /*
 196  * Local Bus LCRR and LBCR regs
 197  */
 198 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 199 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 200 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 201                                 | (0xFF << LBCR_BMT_SHIFT) \
 202                                 | 0xF)  /* 0x0004ff0f */
 203
 204                                 /* LB refresh timer prescal, 266MHz/32 */
 205 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
 206
 207 /* drivers/mtd/nand/nand.c */
 208 #define CONFIG_SYS_NAND_BASE            0xE2800000
 209
 210 #define CONFIG_MTD_PARTITION
 211
 212 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 213 #define CONFIG_NAND_FSL_ELBC 1
 214 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 215 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 216
 217 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
 218                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 219                                 | BR_PS_8               /* 8 bit port */ \
 220                                 | BR_MS_FCM             /* MSEL = FCM */ \
 221                                 | BR_V)                 /* valid */
 222 #define CONFIG_SYS_OR1_PRELIM   \
 223                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 224                                 | OR_FCM_CSCT \
 225                                 | OR_FCM_CST \
 226                                 | OR_FCM_CHT \
 227                                 | OR_FCM_SCY_1 \
 228                                 | OR_FCM_TRLX \
 229                                 | OR_FCM_EHTR)
 230                                 /* 0xFFFF8396 */
 231
 232 /* Still needed for spl_minimal.c */
 233 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 234 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 235
 236 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 237 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 238
 239 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 240 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 241
 242 /* local bus write LED / read status buffer (BCSR) mapping */
 243 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 244 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 245                                         /* map at 0xFA000000 on LCS3 */
 246 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_BCSR_ADDR \
 247                                         | BR_PS_8       /* 8 bit port */ \
 248                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 249                                         | BR_V)         /* valid */
 250                                         /* 0xFA000801 */
 251 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
 252                                         | OR_GPCM_CSNT \
 253                                         | OR_GPCM_ACS_DIV2 \
 254                                         | OR_GPCM_XACS \
 255                                         | OR_GPCM_SCY_15 \
 256                                         | OR_GPCM_TRLX_SET \
 257                                         | OR_GPCM_EHTR_SET \
 258                                         | OR_GPCM_EAD)
 259                                         /* 0xFFFF8FF7 */
 260 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_BCSR_ADDR
 261 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 262
 263 /* Vitesse 7385 */
 264
 265 #ifdef CONFIG_VSC7385_ENET
 266
 267                                         /* VSC7385 Base address on LCS2 */
 268 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 269 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 270
 271 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 272                                         | BR_PS_8       /* 8 bit port */ \
 273                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 274                                         | BR_V)         /* valid */
 275 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
 276                                         | OR_GPCM_CSNT \
 277                                         | OR_GPCM_XACS \
 278                                         | OR_GPCM_SCY_15 \
 279                                         | OR_GPCM_SETA \
 280                                         | OR_GPCM_TRLX_SET \
 281                                         | OR_GPCM_EHTR_SET \
 282                                         | OR_GPCM_EAD)
 283                                         /* 0xFFFE09FF */
 284
 285                                         /* Access window base at VSC7385 base */
 286 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 287 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 288
 289 #endif
 290
 291 #define CONFIG_MPC83XX_GPIO 1
 292
 293 /*
 294  * Serial Port
 295  */
 296 #define CONFIG_SYS_NS16550_SERIAL
 297 #define CONFIG_SYS_NS16550_REG_SIZE     1
 298
 299 #define CONFIG_SYS_BAUDRATE_TABLE       \
 300         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 301
 302 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 303 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 304
 305 /* I2C */
 306 #define CONFIG_SYS_I2C
 307 #define CONFIG_SYS_I2C_FSL
 308 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 309 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 310 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 311 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 312 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 313 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 314 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 315
 316 /*
 317  * General PCI
 318  * Addresses are mapped 1-1.
 319  */
 320 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 321 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 322 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 323 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 324 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 325 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 326 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 327 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 328 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 329
 330 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 331
 332 /*
 333  * TSEC
 334  */
 335
 336 #define CONFIG_GMII                     /* MII PHY management */
 337
 338 #ifdef CONFIG_TSEC1
 339 #define CONFIG_HAS_ETH0
 340 #define CONFIG_TSEC1_NAME       "TSEC0"
 341 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 342 #define TSEC1_PHY_ADDR          0x1c
 343 #define TSEC1_FLAGS             TSEC_GIGABIT
 344 #define TSEC1_PHYIDX            0
 345 #endif
 346
 347 #ifdef CONFIG_TSEC2
 348 #define CONFIG_HAS_ETH1
 349 #define CONFIG_TSEC2_NAME       "TSEC1"
 350 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 351 #define TSEC2_PHY_ADDR          4
 352 #define TSEC2_FLAGS             TSEC_GIGABIT
 353 #define TSEC2_PHYIDX            0
 354 #endif
 355
 356 /* Options are: TSEC[0-1] */
 357 #define CONFIG_ETHPRIME                 "TSEC1"
 358
 359 /*
 360  * Configure on-board RTC
 361  */
 362 #define CONFIG_RTC_DS1337
 363 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 364
 365 /*
 366  * Environment
 367  */
 368 #if !defined(CONFIG_SYS_RAMBOOT)
 369         #define CONFIG_ENV_ADDR         \
 370                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 371         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 372         #define CONFIG_ENV_SIZE         0x2000
 373
 374 /* Address and size of Redundant Environment Sector */
 375 #else
 376         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 377         #define CONFIG_ENV_SIZE         0x2000
 378 #endif
 379
 380 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 381 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 382
 383 /*
 384  * BOOTP options
 385  */
 386 #define CONFIG_BOOTP_BOOTFILESIZE
 387
 388 /*
 389  * Command line configuration.
 390  */
 391
 392 /*
 393  * Miscellaneous configurable options
 394  */
 395 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 396 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 397
 398                                 /* Boot Argument Buffer Size */
 399 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 400
 401 /*
 402  * For booting Linux, the board info and command line data
 403  * have to be in the first 256 MB of memory, since this is
 404  * the maximum mapped by the Linux kernel during initialization.
 405  */
 406                                 /* Initial Memory map for Linux*/
 407 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 408 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 409
 410 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 411
 412 #ifdef CONFIG_SYS_66MHZ
 413
 414 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
 415 /* 0x62040000 */
 416 #define CONFIG_SYS_HRCW_LOW (\
 417         0x20000000 /* reserved, must be set */ |\
 418         HRCWL_DDRCM |\
 419         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 420         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 421         HRCWL_CSB_TO_CLKIN_2X1 |\
 422         HRCWL_CORE_TO_CSB_2X1)
 423
 424 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
 425
 426 #elif defined(CONFIG_SYS_33MHZ)
 427
 428 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
 429 /* 0x65040000 */
 430 #define CONFIG_SYS_HRCW_LOW (\
 431         0x20000000 /* reserved, must be set */ |\
 432         HRCWL_DDRCM |\
 433         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 434         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 435         HRCWL_CSB_TO_CLKIN_5X1 |\
 436         HRCWL_CORE_TO_CSB_2X1)
 437
 438 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
 439
 440 #endif
 441
 442 #define CONFIG_SYS_HRCW_HIGH_BASE (\
 443         HRCWH_PCI_HOST |\
 444         HRCWH_PCI1_ARBITER_ENABLE |\
 445         HRCWH_CORE_ENABLE |\
 446         HRCWH_BOOTSEQ_DISABLE |\
 447         HRCWH_SW_WATCHDOG_DISABLE |\
 448         HRCWH_TSEC1M_IN_RGMII |\
 449         HRCWH_TSEC2M_IN_RGMII |\
 450         HRCWH_BIG_ENDIAN)
 451
 452 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 453                        HRCWH_FROM_0X00000100 |\
 454                        HRCWH_ROM_LOC_LOCAL_16BIT |\
 455                        HRCWH_RL_EXT_LEGACY)
 456
 457 /* System IO Config */
 458 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 459                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 460 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 461
 462 #define CONFIG_SYS_HID0_INIT    0x000000000
 463 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 464                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 465                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 466
 467 #define CONFIG_SYS_HID2 HID2_HBE
 468
 469 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 470
 471 /* DDR @ 0x00000000 */
 472 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 473 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 474                                 | BATU_BL_256M \
 475                                 | BATU_VS \
 476                                 | BATU_VP)
 477
 478 /* PCI @ 0x80000000 */
 479 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 480 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 481                                 | BATU_BL_256M \
 482                                 | BATU_VS \
 483                                 | BATU_VP)
 484 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 485                                 | BATL_PP_RW \
 486                                 | BATL_CACHEINHIBIT \
 487                                 | BATL_GUARDEDSTORAGE)
 488 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 489                                 | BATU_BL_256M \
 490                                 | BATU_VS \
 491                                 | BATU_VP)
 492
 493 /* PCI2 not supported on 8313 */
 494 #define CONFIG_SYS_IBAT3L       (0)
 495 #define CONFIG_SYS_IBAT3U       (0)
 496 #define CONFIG_SYS_IBAT4L       (0)
 497 #define CONFIG_SYS_IBAT4U       (0)
 498
 499 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 500 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 501                                 | BATL_PP_RW \
 502                                 | BATL_CACHEINHIBIT \
 503                                 | BATL_GUARDEDSTORAGE)
 504 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 505                                 | BATU_BL_256M \
 506                                 | BATU_VS \
 507                                 | BATU_VP)
 508
 509 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 510 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 511 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 512
 513 #define CONFIG_SYS_IBAT7L       (0)
 514 #define CONFIG_SYS_IBAT7U       (0)
 515
 516 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 517 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 518 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 519 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 520 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 521 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 522 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 523 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 524 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 525 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 526 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 527 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 528 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 529 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 530 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 531 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 532
 533 /*
 534  * Environment Configuration
 535  */
 536 #define CONFIG_ENV_OVERWRITE
 537
 538 #define CONFIG_NETDEV           "eth1"
 539
 540 #define CONFIG_HOSTNAME         "mpc8313erdb"
 541 #define CONFIG_ROOTPATH         "/nfs/root/path"
 542 #define CONFIG_BOOTFILE         "uImage"
 543                                 /* U-Boot image on TFTP server */
 544 #define CONFIG_UBOOTPATH        "u-boot.bin"
 545 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 546
 547                                 /* default location for tftp and bootm */
 548 #define CONFIG_LOADADDR         800000
 549
 550 #define CONFIG_EXTRA_ENV_SETTINGS \
 551         "netdev=" CONFIG_NETDEV "\0"                                    \
 552         "ethprime=TSEC1\0"                                              \
 553         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 554         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 555                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 556                         " +$filesize; " \
 557                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 558                         " +$filesize; " \
 559                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 560                         " $filesize; "  \
 561                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 562                         " +$filesize; " \
 563                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 564                         " $filesize\0"  \
 565         "fdtaddr=780000\0"                                              \
 566         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 567         "console=ttyS0\0"                                               \
 568         "setbootargs=setenv bootargs "                                  \
 569                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 570         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 571                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 572                                                         "$netdev:off " \
 573                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 574
 575 #define CONFIG_NFSBOOTCOMMAND                                           \
 576         "setenv rootdev /dev/nfs;"                                      \
 577         "run setbootargs;"                                              \
 578         "run setipargs;"                                                \
 579         "tftp $loadaddr $bootfile;"                                     \
 580         "tftp $fdtaddr $fdtfile;"                                       \
 581         "bootm $loadaddr - $fdtaddr"
 582
 583 #define CONFIG_RAMBOOTCOMMAND                                           \
 584         "setenv rootdev /dev/ram;"                                      \
 585         "run setbootargs;"                                              \
 586         "tftp $ramdiskaddr $ramdiskfile;"                               \
 587         "tftp $loadaddr $bootfile;"                                     \
 588         "tftp $fdtaddr $fdtfile;"                                       \
 589         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 590
 591 #endif  /* __CONFIG_H */