1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
6 * mpc8313epb board configuration file
13 * High Level Configuration Options
17 #ifndef CONFIG_SYS_MONITOR_BASE
18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
21 #define CONFIG_PCI_INDIRECT_BRIDGE
29 #define CONFIG_VSC7385_ENET
32 /* Early revs of this board will lock up hard when attempting
33 * to access the PMC registers, unless a JTAG debugger is
34 * connected, or some resistor modifications are made.
36 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
39 * Device configurations
44 #ifdef CONFIG_VSC7385_ENET
48 /* The flash address and size of the VSC7385 firmware image */
49 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
50 #define CONFIG_VSC7385_IMAGE_SIZE 8192
57 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
60 * Manually set up DDR parameters, as this board does not
61 * seem to have the SPD connected to I2C.
63 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
64 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
65 | CSCONFIG_ODT_RD_NEVER \
66 | CSCONFIG_ODT_WR_ONLY_CURRENT \
67 | CSCONFIG_ROW_BIT_13 \
68 | CSCONFIG_COL_BIT_10)
71 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
72 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
73 | (0 << TIMING_CFG0_WRT_SHIFT) \
74 | (0 << TIMING_CFG0_RRT_SHIFT) \
75 | (0 << TIMING_CFG0_WWT_SHIFT) \
76 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
77 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
78 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
79 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
81 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
82 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
83 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
84 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
85 | (10 << TIMING_CFG1_REFREC_SHIFT) \
86 | (3 << TIMING_CFG1_WRREC_SHIFT) \
87 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
88 | (2 << TIMING_CFG1_WRTORD_SHIFT))
90 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
91 | (5 << TIMING_CFG2_CPO_SHIFT) \
92 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
93 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
94 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
95 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
96 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
97 /* 0x129048c6 */ /* P9-45,may need tuning */
98 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
99 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
101 #if defined(CONFIG_DDR_2T_TIMING)
102 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
103 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
108 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
109 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
113 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
114 /* set burst length to 8 for 32-bit data path */
115 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
116 | (0x0632 << SDRAM_MODE_SD_SHIFT))
118 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
120 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
122 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
128 * FLASH on the Local Bus
130 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
131 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
132 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
133 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
135 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
136 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
138 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
139 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
141 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
142 !defined(CONFIG_SPL_BUILD)
143 #define CONFIG_SYS_RAMBOOT
146 #define CONFIG_SYS_INIT_RAM_LOCK 1
147 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
148 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
150 #define CONFIG_SYS_GBL_DATA_OFFSET \
151 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
152 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
154 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
155 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
156 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
158 /* drivers/mtd/nand/nand.c */
159 #define CONFIG_SYS_NAND_BASE 0xE2800000
161 #define CONFIG_MTD_PARTITION
163 #define CONFIG_SYS_MAX_NAND_DEVICE 1
164 #define CONFIG_NAND_FSL_ELBC 1
165 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
166 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
168 /* Still needed for spl_minimal.c */
169 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
170 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
172 /* local bus write LED / read status buffer (BCSR) mapping */
173 #define CONFIG_SYS_BCSR_ADDR 0xFA000000
174 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
175 /* map at 0xFA000000 on LCS3 */
178 #ifdef CONFIG_VSC7385_ENET
180 /* VSC7385 Base address on LCS2 */
181 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
182 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
187 #define CONFIG_MPC83XX_GPIO 1
192 #define CONFIG_SYS_NS16550_SERIAL
193 #define CONFIG_SYS_NS16550_REG_SIZE 1
195 #define CONFIG_SYS_BAUDRATE_TABLE \
196 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
198 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
199 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
202 #define CONFIG_SYS_I2C
203 #define CONFIG_SYS_I2C_FSL
204 #define CONFIG_SYS_FSL_I2C_SPEED 400000
205 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
206 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
207 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
208 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
209 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
210 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
214 * Addresses are mapped 1-1.
216 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
217 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
218 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
219 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
220 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
221 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
222 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
223 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
224 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
226 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
232 #define CONFIG_GMII /* MII PHY management */
235 #define CONFIG_HAS_ETH0
236 #define CONFIG_TSEC1_NAME "TSEC0"
237 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
238 #define TSEC1_PHY_ADDR 0x1c
239 #define TSEC1_FLAGS TSEC_GIGABIT
240 #define TSEC1_PHYIDX 0
244 #define CONFIG_HAS_ETH1
245 #define CONFIG_TSEC2_NAME "TSEC1"
246 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
247 #define TSEC2_PHY_ADDR 4
248 #define TSEC2_FLAGS TSEC_GIGABIT
249 #define TSEC2_PHYIDX 0
252 /* Options are: TSEC[0-1] */
253 #define CONFIG_ETHPRIME "TSEC1"
256 * Configure on-board RTC
258 #define CONFIG_RTC_DS1337
259 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
264 #if !defined(CONFIG_SYS_RAMBOOT)
265 /* Address and size of Redundant Environment Sector */
268 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
269 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
274 #define CONFIG_BOOTP_BOOTFILESIZE
277 * Command line configuration.
281 * Miscellaneous configurable options
283 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
284 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
286 /* Boot Argument Buffer Size */
287 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
290 * For booting Linux, the board info and command line data
291 * have to be in the first 256 MB of memory, since this is
292 * the maximum mapped by the Linux kernel during initialization.
294 /* Initial Memory map for Linux*/
295 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
296 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
298 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
300 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
302 /* System IO Config */
303 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
304 /* Enable Internal USB Phy and GPIO on LCD Connector */
305 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
308 * Environment Configuration
310 #define CONFIG_ENV_OVERWRITE
312 #define CONFIG_NETDEV "eth1"
314 #define CONFIG_HOSTNAME "mpc8313erdb"
315 #define CONFIG_ROOTPATH "/nfs/root/path"
316 #define CONFIG_BOOTFILE "uImage"
317 /* U-Boot image on TFTP server */
318 #define CONFIG_UBOOTPATH "u-boot.bin"
319 #define CONFIG_FDTFILE "mpc8313erdb.dtb"
321 /* default location for tftp and bootm */
322 #define CONFIG_LOADADDR 800000
324 #define CONFIG_EXTRA_ENV_SETTINGS \
325 "netdev=" CONFIG_NETDEV "\0" \
327 "uboot=" CONFIG_UBOOTPATH "\0" \
328 "tftpflash=tftpboot $loadaddr $uboot; " \
329 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
331 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
333 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
335 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
337 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
340 "fdtfile=" CONFIG_FDTFILE "\0" \
342 "setbootargs=setenv bootargs " \
343 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
344 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
345 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
347 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
349 #define CONFIG_NFSBOOTCOMMAND \
350 "setenv rootdev /dev/nfs;" \
353 "tftp $loadaddr $bootfile;" \
354 "tftp $fdtaddr $fdtfile;" \
355 "bootm $loadaddr - $fdtaddr"
357 #define CONFIG_RAMBOOTCOMMAND \
358 "setenv rootdev /dev/ram;" \
360 "tftp $ramdiskaddr $ramdiskfile;" \
361 "tftp $loadaddr $bootfile;" \
362 "tftp $fdtaddr $fdtfile;" \
363 "bootm $loadaddr $ramdiskaddr $fdtaddr"
365 #endif /* __CONFIG_H */