include/configs/MPC8313ERDB_NOR.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   4  */
   5 /*
   6  * mpc8313epb board configuration file
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 #include <linux/stringify.h>
  22 #define CONFIG_PCI_INDIRECT_BRIDGE
  23
  24 /*
  25  * On-board devices
  26  *
  27  * TSEC1 is VSC switch
  28  * TSEC2 is SoC TSEC
  29  */
  30 #define CONFIG_VSC7385_ENET
  31 #define CONFIG_TSEC2
  32
  33 /* Early revs of this board will lock up hard when attempting
  34  * to access the PMC registers, unless a JTAG debugger is
  35  * connected, or some resistor modifications are made.
  36  */
  37 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  38
  39 /*
  40  * Device configurations
  41  */
  42
  43 /* Vitesse 7385 */
  44
  45 #ifdef CONFIG_VSC7385_ENET
  46
  47 #define CONFIG_TSEC1
  48
  49 /* The flash address and size of the VSC7385 firmware image */
  50 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  51 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  52
  53 #endif
  54
  55 /*
  56  * DDR Setup
  57  */
  58 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory*/
  59
  60 /*
  61  * Manually set up DDR parameters, as this board does not
  62  * seem to have the SPD connected to I2C.
  63  */
  64 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
  65 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  66                                 | CSCONFIG_ODT_RD_NEVER \
  67                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  68                                 | CSCONFIG_ROW_BIT_13 \
  69                                 | CSCONFIG_COL_BIT_10)
  70                                 /* 0x80010102 */
  71
  72 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  73 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  74                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  75                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  76                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  77                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  78                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  79                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  80                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  81                                 /* 0x00220802 */
  82 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  83                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  84                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  85                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  86                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
  87                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
  88                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  89                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  90                                 /* 0x3835a322 */
  91 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  92                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
  93                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  94                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  95                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  96                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  97                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
  98                                 /* 0x129048c6 */ /* P9-45,may need tuning */
  99 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 100                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 101                                 /* 0x05100500 */
 102 #if defined(CONFIG_DDR_2T_TIMING)
 103 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 104                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 105                                 | SDRAM_CFG_DBW_32 \
 106                                 | SDRAM_CFG_2T_EN)
 107                                 /* 0x43088000 */
 108 #else
 109 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 110                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 111                                 | SDRAM_CFG_DBW_32)
 112                                 /* 0x43080000 */
 113 #endif
 114 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 115 /* set burst length to 8 for 32-bit data path */
 116 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 117                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 118                                 /* 0x44480632 */
 119 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 120
 121 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 122                                 /*0x02000000*/
 123 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 124                                 | DDRCDR_PZ_NOMZ \
 125                                 | DDRCDR_NZ_NOMZ \
 126                                 | DDRCDR_M_ODR)
 127
 128 /*
 129  * FLASH on the Local Bus
 130  */
 131 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 132 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 133 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 134 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 135
 136 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 137 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 138
 139 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 140 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 141
 142 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 143         !defined(CONFIG_SPL_BUILD)
 144 #define CONFIG_SYS_RAMBOOT
 145 #endif
 146
 147 #define CONFIG_SYS_INIT_RAM_LOCK        1
 148 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 149 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 150
 151 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 152                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 153 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 154
 155 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 156 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 157 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 158
 159 /* drivers/mtd/nand/nand.c */
 160 #define CONFIG_SYS_NAND_BASE            0xE2800000
 161
 162 #define CONFIG_MTD_PARTITION
 163
 164 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 165 #define CONFIG_NAND_FSL_ELBC 1
 166 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 167 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 168
 169 /* Still needed for spl_minimal.c */
 170 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 171 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 172
 173 /* local bus write LED / read status buffer (BCSR) mapping */
 174 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 175 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 176                                         /* map at 0xFA000000 on LCS3 */
 177 /* Vitesse 7385 */
 178
 179 #ifdef CONFIG_VSC7385_ENET
 180
 181                                         /* VSC7385 Base address on LCS2 */
 182 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 183 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 184
 185
 186 #endif
 187
 188 #define CONFIG_MPC83XX_GPIO 1
 189
 190 /*
 191  * Serial Port
 192  */
 193 #define CONFIG_SYS_NS16550_SERIAL
 194 #define CONFIG_SYS_NS16550_REG_SIZE     1
 195
 196 #define CONFIG_SYS_BAUDRATE_TABLE       \
 197         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 198
 199 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 200 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 201
 202 /* I2C */
 203 #define CONFIG_SYS_I2C
 204 #define CONFIG_SYS_I2C_FSL
 205 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 206 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 207 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 208 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 209 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 210 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 211 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 212
 213 /*
 214  * General PCI
 215  * Addresses are mapped 1-1.
 216  */
 217 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 218 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 219 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 220 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 221 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 222 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 223 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 224 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 225 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 226
 227 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 228
 229 /*
 230  * TSEC
 231  */
 232
 233 #define CONFIG_GMII                     /* MII PHY management */
 234
 235 #ifdef CONFIG_TSEC1
 236 #define CONFIG_HAS_ETH0
 237 #define CONFIG_TSEC1_NAME       "TSEC0"
 238 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 239 #define TSEC1_PHY_ADDR          0x1c
 240 #define TSEC1_FLAGS             TSEC_GIGABIT
 241 #define TSEC1_PHYIDX            0
 242 #endif
 243
 244 #ifdef CONFIG_TSEC2
 245 #define CONFIG_HAS_ETH1
 246 #define CONFIG_TSEC2_NAME       "TSEC1"
 247 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 248 #define TSEC2_PHY_ADDR          4
 249 #define TSEC2_FLAGS             TSEC_GIGABIT
 250 #define TSEC2_PHYIDX            0
 251 #endif
 252
 253 /* Options are: TSEC[0-1] */
 254 #define CONFIG_ETHPRIME                 "TSEC1"
 255
 256 /*
 257  * Configure on-board RTC
 258  */
 259 #define CONFIG_RTC_DS1337
 260 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 261
 262 /*
 263  * Environment
 264  */
 265 #if !defined(CONFIG_SYS_RAMBOOT)
 266 /* Address and size of Redundant Environment Sector */
 267 #endif
 268
 269 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 270 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 271
 272 /*
 273  * BOOTP options
 274  */
 275 #define CONFIG_BOOTP_BOOTFILESIZE
 276
 277 /*
 278  * Command line configuration.
 279  */
 280
 281 /*
 282  * Miscellaneous configurable options
 283  */
 284 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 285 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 286
 287                                 /* Boot Argument Buffer Size */
 288 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 289
 290 /*
 291  * For booting Linux, the board info and command line data
 292  * have to be in the first 256 MB of memory, since this is
 293  * the maximum mapped by the Linux kernel during initialization.
 294  */
 295                                 /* Initial Memory map for Linux*/
 296 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 297 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 298
 299 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 300
 301 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
 302
 303 /* System IO Config */
 304 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 305                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 306 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 307
 308 /*
 309  * Environment Configuration
 310  */
 311 #define CONFIG_ENV_OVERWRITE
 312
 313 #define CONFIG_NETDEV           "eth1"
 314
 315 #define CONFIG_HOSTNAME         "mpc8313erdb"
 316 #define CONFIG_ROOTPATH         "/nfs/root/path"
 317 #define CONFIG_BOOTFILE         "uImage"
 318                                 /* U-Boot image on TFTP server */
 319 #define CONFIG_UBOOTPATH        "u-boot.bin"
 320 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 321
 322                                 /* default location for tftp and bootm */
 323 #define CONFIG_LOADADDR         800000
 324
 325 #define CONFIG_EXTRA_ENV_SETTINGS \
 326         "netdev=" CONFIG_NETDEV "\0"                                    \
 327         "ethprime=TSEC1\0"                                              \
 328         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 329         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 330                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 331                         " +$filesize; " \
 332                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 333                         " +$filesize; " \
 334                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 335                         " $filesize; "  \
 336                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 337                         " +$filesize; " \
 338                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 339                         " $filesize\0"  \
 340         "fdtaddr=780000\0"                                              \
 341         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 342         "console=ttyS0\0"                                               \
 343         "setbootargs=setenv bootargs "                                  \
 344                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 345         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 346                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 347                                                         "$netdev:off " \
 348                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 349
 350 #define CONFIG_NFSBOOTCOMMAND                                           \
 351         "setenv rootdev /dev/nfs;"                                      \
 352         "run setbootargs;"                                              \
 353         "run setipargs;"                                                \
 354         "tftp $loadaddr $bootfile;"                                     \
 355         "tftp $fdtaddr $fdtfile;"                                       \
 356         "bootm $loadaddr - $fdtaddr"
 357
 358 #define CONFIG_RAMBOOTCOMMAND                                           \
 359         "setenv rootdev /dev/ram;"                                      \
 360         "run setbootargs;"                                              \
 361         "tftp $ramdiskaddr $ramdiskfile;"                               \
 362         "tftp $loadaddr $bootfile;"                                     \
 363         "tftp $fdtaddr $fdtfile;"                                       \
 364         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 365
 366 #endif  /* __CONFIG_H */