1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
6 * mpc8313epb board configuration file
13 * High Level Configuration Options
17 #define CONFIG_SPL_INIT_MINIMAL
18 #define CONFIG_SPL_FLUSH_IMAGE
19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
20 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
22 #ifdef CONFIG_SPL_BUILD
23 #define CONFIG_NS16550_MIN_FUNCTIONS
26 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
27 #define CONFIG_SPL_MAX_SIZE (4 * 1024)
28 #define CONFIG_SPL_PAD_TO 0x4000
30 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
31 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
32 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
33 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
34 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
35 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
37 #ifdef CONFIG_SPL_BUILD
38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
41 #ifndef CONFIG_SYS_MONITOR_BASE
42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
45 #define CONFIG_PCI_INDIRECT_BRIDGE
46 #define CONFIG_FSL_ELBC 1
54 #define CONFIG_VSC7385_ENET
57 #if !defined(CONFIG_SPL_BUILD)
58 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
61 #define CONFIG_SYS_MEMTEST_START 0x00001000
62 #define CONFIG_SYS_MEMTEST_END 0x07f00000
64 /* Early revs of this board will lock up hard when attempting
65 * to access the PMC registers, unless a JTAG debugger is
66 * connected, or some resistor modifications are made.
68 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
71 * Device configurations
76 #ifdef CONFIG_VSC7385_ENET
80 /* The flash address and size of the VSC7385 firmware image */
81 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
82 #define CONFIG_VSC7385_IMAGE_SIZE 8192
89 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
90 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
93 * Manually set up DDR parameters, as this board does not
94 * seem to have the SPD connected to I2C.
96 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
97 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
98 | CSCONFIG_ODT_RD_NEVER \
99 | CSCONFIG_ODT_WR_ONLY_CURRENT \
100 | CSCONFIG_ROW_BIT_13 \
101 | CSCONFIG_COL_BIT_10)
104 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
105 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
106 | (0 << TIMING_CFG0_WRT_SHIFT) \
107 | (0 << TIMING_CFG0_RRT_SHIFT) \
108 | (0 << TIMING_CFG0_WWT_SHIFT) \
109 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
110 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
111 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
112 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
114 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
115 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
116 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
117 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
118 | (10 << TIMING_CFG1_REFREC_SHIFT) \
119 | (3 << TIMING_CFG1_WRREC_SHIFT) \
120 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
121 | (2 << TIMING_CFG1_WRTORD_SHIFT))
123 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
124 | (5 << TIMING_CFG2_CPO_SHIFT) \
125 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
126 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
127 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
128 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
129 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
130 /* 0x129048c6 */ /* P9-45,may need tuning */
131 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
132 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
134 #if defined(CONFIG_DDR_2T_TIMING)
135 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
136 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
141 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
142 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
146 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
147 /* set burst length to 8 for 32-bit data path */
148 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
149 | (0x0632 << SDRAM_MODE_SD_SHIFT))
151 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
153 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
155 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
161 * FLASH on the Local Bus
163 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
164 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
165 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
167 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
168 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
170 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
171 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
173 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
174 !defined(CONFIG_SPL_BUILD)
175 #define CONFIG_SYS_RAMBOOT
178 #define CONFIG_SYS_INIT_RAM_LOCK 1
179 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
180 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
182 #define CONFIG_SYS_GBL_DATA_OFFSET \
183 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
184 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
186 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
187 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
188 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
191 * Local Bus LCRR and LBCR regs
193 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
194 | (0xFF << LBCR_BMT_SHIFT) \
195 | 0xF) /* 0x0004ff0f */
197 /* LB refresh timer prescal, 266MHz/32 */
198 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
200 /* drivers/mtd/nand/raw/nand.c */
201 #if defined(CONFIG_SPL_BUILD)
202 #define CONFIG_SYS_NAND_BASE 0xFFF00000
204 #define CONFIG_SYS_NAND_BASE 0xE2800000
207 #define CONFIG_MTD_PARTITION
209 #define CONFIG_SYS_MAX_NAND_DEVICE 1
210 #define CONFIG_NAND_FSL_ELBC 1
211 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
212 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
214 /* Still needed for spl_minimal.c */
215 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
216 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
218 /* local bus write LED / read status buffer (BCSR) mapping */
219 #define CONFIG_SYS_BCSR_ADDR 0xFA000000
220 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
221 /* map at 0xFA000000 on LCS3 */
225 #ifdef CONFIG_VSC7385_ENET
227 /* VSC7385 Base address on LCS2 */
228 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
229 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
234 #define CONFIG_MPC83XX_GPIO 1
239 #define CONFIG_SYS_NS16550_SERIAL
240 #define CONFIG_SYS_NS16550_REG_SIZE 1
242 #define CONFIG_SYS_BAUDRATE_TABLE \
243 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
245 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
246 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
249 #define CONFIG_SYS_I2C
250 #define CONFIG_SYS_I2C_FSL
251 #define CONFIG_SYS_FSL_I2C_SPEED 400000
252 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
253 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
254 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
255 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
256 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
257 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
261 * Addresses are mapped 1-1.
263 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
264 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
265 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
266 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
267 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
268 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
269 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
270 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
271 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
273 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
279 #define CONFIG_GMII /* MII PHY management */
282 #define CONFIG_HAS_ETH0
283 #define CONFIG_TSEC1_NAME "TSEC0"
284 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
285 #define TSEC1_PHY_ADDR 0x1c
286 #define TSEC1_FLAGS TSEC_GIGABIT
287 #define TSEC1_PHYIDX 0
291 #define CONFIG_HAS_ETH1
292 #define CONFIG_TSEC2_NAME "TSEC1"
293 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
294 #define TSEC2_PHY_ADDR 4
295 #define TSEC2_FLAGS TSEC_GIGABIT
296 #define TSEC2_PHYIDX 0
299 /* Options are: TSEC[0-1] */
300 #define CONFIG_ETHPRIME "TSEC1"
303 * Configure on-board RTC
305 #define CONFIG_RTC_DS1337
306 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
311 #define CONFIG_ENV_OFFSET (512 * 1024)
312 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
313 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
314 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
315 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
316 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
318 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
319 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
324 #define CONFIG_BOOTP_BOOTFILESIZE
327 * Command line configuration.
331 * Miscellaneous configurable options
333 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
334 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
336 /* Boot Argument Buffer Size */
337 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
340 * For booting Linux, the board info and command line data
341 * have to be in the first 256 MB of memory, since this is
342 * the maximum mapped by the Linux kernel during initialization.
344 /* Initial Memory map for Linux*/
345 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
346 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
348 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
350 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
352 /* System IO Config */
353 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
354 /* Enable Internal USB Phy and GPIO on LCD Connector */
355 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
358 * Environment Configuration
360 #define CONFIG_ENV_OVERWRITE
362 #define CONFIG_NETDEV "eth1"
364 #define CONFIG_HOSTNAME "mpc8313erdb"
365 #define CONFIG_ROOTPATH "/nfs/root/path"
366 #define CONFIG_BOOTFILE "uImage"
367 /* U-Boot image on TFTP server */
368 #define CONFIG_UBOOTPATH "u-boot.bin"
369 #define CONFIG_FDTFILE "mpc8313erdb.dtb"
371 /* default location for tftp and bootm */
372 #define CONFIG_LOADADDR 800000
374 #define CONFIG_EXTRA_ENV_SETTINGS \
375 "netdev=" CONFIG_NETDEV "\0" \
377 "uboot=" CONFIG_UBOOTPATH "\0" \
378 "tftpflash=tftpboot $loadaddr $uboot; " \
379 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
381 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
383 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
385 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
387 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
390 "fdtfile=" CONFIG_FDTFILE "\0" \
392 "setbootargs=setenv bootargs " \
393 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
394 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
395 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
397 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
399 #define CONFIG_NFSBOOTCOMMAND \
400 "setenv rootdev /dev/nfs;" \
403 "tftp $loadaddr $bootfile;" \
404 "tftp $fdtaddr $fdtfile;" \
405 "bootm $loadaddr - $fdtaddr"
407 #define CONFIG_RAMBOOTCOMMAND \
408 "setenv rootdev /dev/ram;" \
410 "tftp $ramdiskaddr $ramdiskfile;" \
411 "tftp $loadaddr $bootfile;" \
412 "tftp $fdtaddr $fdtfile;" \
413 "bootm $loadaddr $ramdiskaddr $fdtaddr"
415 #endif /* __CONFIG_H */