1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
6 * mpc8313epb board configuration file
13 * High Level Configuration Options
17 #define CONFIG_SPL_INIT_MINIMAL
18 #define CONFIG_SPL_FLUSH_IMAGE
19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
20 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
22 #ifdef CONFIG_SPL_BUILD
23 #define CONFIG_NS16550_MIN_FUNCTIONS
26 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
27 #define CONFIG_SPL_MAX_SIZE (4 * 1024)
28 #define CONFIG_SPL_PAD_TO 0x4000
30 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
31 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
32 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
33 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
34 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
35 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
37 #ifdef CONFIG_SPL_BUILD
38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
41 #ifndef CONFIG_SYS_MONITOR_BASE
42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
45 #define CONFIG_PCI_INDIRECT_BRIDGE
46 #define CONFIG_FSL_ELBC 1
54 #define CONFIG_VSC7385_ENET
57 #if !defined(CONFIG_SPL_BUILD)
58 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
61 #define CONFIG_SYS_MEMTEST_START 0x00001000
62 #define CONFIG_SYS_MEMTEST_END 0x07f00000
64 /* Early revs of this board will lock up hard when attempting
65 * to access the PMC registers, unless a JTAG debugger is
66 * connected, or some resistor modifications are made.
68 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
70 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
71 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
74 * Device configurations
79 #ifdef CONFIG_VSC7385_ENET
83 /* The flash address and size of the VSC7385 firmware image */
84 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
85 #define CONFIG_VSC7385_IMAGE_SIZE 8192
92 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
93 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
94 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
97 * Manually set up DDR parameters, as this board does not
98 * seem to have the SPD connected to I2C.
100 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
101 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
102 | CSCONFIG_ODT_RD_NEVER \
103 | CSCONFIG_ODT_WR_ONLY_CURRENT \
104 | CSCONFIG_ROW_BIT_13 \
105 | CSCONFIG_COL_BIT_10)
108 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
109 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
110 | (0 << TIMING_CFG0_WRT_SHIFT) \
111 | (0 << TIMING_CFG0_RRT_SHIFT) \
112 | (0 << TIMING_CFG0_WWT_SHIFT) \
113 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
114 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
115 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
116 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
118 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
119 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
120 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
121 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
122 | (10 << TIMING_CFG1_REFREC_SHIFT) \
123 | (3 << TIMING_CFG1_WRREC_SHIFT) \
124 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
125 | (2 << TIMING_CFG1_WRTORD_SHIFT))
127 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
128 | (5 << TIMING_CFG2_CPO_SHIFT) \
129 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
130 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
131 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
132 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
133 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
134 /* 0x129048c6 */ /* P9-45,may need tuning */
135 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
136 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
138 #if defined(CONFIG_DDR_2T_TIMING)
139 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
140 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
145 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
146 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
150 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
151 /* set burst length to 8 for 32-bit data path */
152 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
153 | (0x0632 << SDRAM_MODE_SD_SHIFT))
155 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
157 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
159 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
165 * FLASH on the Local Bus
167 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
168 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
169 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
171 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
172 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
174 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
175 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
177 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
178 !defined(CONFIG_SPL_BUILD)
179 #define CONFIG_SYS_RAMBOOT
182 #define CONFIG_SYS_INIT_RAM_LOCK 1
183 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
184 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
186 #define CONFIG_SYS_GBL_DATA_OFFSET \
187 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
188 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
190 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
191 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
192 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
195 * Local Bus LCRR and LBCR regs
197 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
198 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
199 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
200 | (0xFF << LBCR_BMT_SHIFT) \
201 | 0xF) /* 0x0004ff0f */
203 /* LB refresh timer prescal, 266MHz/32 */
204 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
206 /* drivers/mtd/nand/raw/nand.c */
207 #if defined(CONFIG_SPL_BUILD)
208 #define CONFIG_SYS_NAND_BASE 0xFFF00000
210 #define CONFIG_SYS_NAND_BASE 0xE2800000
213 #define CONFIG_MTD_PARTITION
215 #define CONFIG_SYS_MAX_NAND_DEVICE 1
216 #define CONFIG_NAND_FSL_ELBC 1
217 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
218 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
220 /* Still needed for spl_minimal.c */
221 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
222 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
224 /* local bus write LED / read status buffer (BCSR) mapping */
225 #define CONFIG_SYS_BCSR_ADDR 0xFA000000
226 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
227 /* map at 0xFA000000 on LCS3 */
231 #ifdef CONFIG_VSC7385_ENET
233 /* VSC7385 Base address on LCS2 */
234 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
235 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
240 #define CONFIG_MPC83XX_GPIO 1
245 #define CONFIG_SYS_NS16550_SERIAL
246 #define CONFIG_SYS_NS16550_REG_SIZE 1
248 #define CONFIG_SYS_BAUDRATE_TABLE \
249 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
251 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
252 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
255 #define CONFIG_SYS_I2C
256 #define CONFIG_SYS_I2C_FSL
257 #define CONFIG_SYS_FSL_I2C_SPEED 400000
258 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
259 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
260 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
261 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
262 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
263 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
267 * Addresses are mapped 1-1.
269 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
270 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
271 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
272 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
273 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
274 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
275 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
276 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
277 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
279 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
285 #define CONFIG_GMII /* MII PHY management */
288 #define CONFIG_HAS_ETH0
289 #define CONFIG_TSEC1_NAME "TSEC0"
290 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
291 #define TSEC1_PHY_ADDR 0x1c
292 #define TSEC1_FLAGS TSEC_GIGABIT
293 #define TSEC1_PHYIDX 0
297 #define CONFIG_HAS_ETH1
298 #define CONFIG_TSEC2_NAME "TSEC1"
299 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
300 #define TSEC2_PHY_ADDR 4
301 #define TSEC2_FLAGS TSEC_GIGABIT
302 #define TSEC2_PHYIDX 0
305 /* Options are: TSEC[0-1] */
306 #define CONFIG_ETHPRIME "TSEC1"
309 * Configure on-board RTC
311 #define CONFIG_RTC_DS1337
312 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
317 #define CONFIG_ENV_OFFSET (512 * 1024)
318 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
319 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
320 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
321 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
322 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
324 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
325 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
330 #define CONFIG_BOOTP_BOOTFILESIZE
333 * Command line configuration.
337 * Miscellaneous configurable options
339 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
340 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
342 /* Boot Argument Buffer Size */
343 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
346 * For booting Linux, the board info and command line data
347 * have to be in the first 256 MB of memory, since this is
348 * the maximum mapped by the Linux kernel during initialization.
350 /* Initial Memory map for Linux*/
351 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
352 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
354 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
356 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
358 /* System IO Config */
359 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
360 /* Enable Internal USB Phy and GPIO on LCD Connector */
361 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
364 * Environment Configuration
366 #define CONFIG_ENV_OVERWRITE
368 #define CONFIG_NETDEV "eth1"
370 #define CONFIG_HOSTNAME "mpc8313erdb"
371 #define CONFIG_ROOTPATH "/nfs/root/path"
372 #define CONFIG_BOOTFILE "uImage"
373 /* U-Boot image on TFTP server */
374 #define CONFIG_UBOOTPATH "u-boot.bin"
375 #define CONFIG_FDTFILE "mpc8313erdb.dtb"
377 /* default location for tftp and bootm */
378 #define CONFIG_LOADADDR 800000
380 #define CONFIG_EXTRA_ENV_SETTINGS \
381 "netdev=" CONFIG_NETDEV "\0" \
383 "uboot=" CONFIG_UBOOTPATH "\0" \
384 "tftpflash=tftpboot $loadaddr $uboot; " \
385 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
387 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
389 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
391 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
393 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
396 "fdtfile=" CONFIG_FDTFILE "\0" \
398 "setbootargs=setenv bootargs " \
399 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
400 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
401 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
403 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
405 #define CONFIG_NFSBOOTCOMMAND \
406 "setenv rootdev /dev/nfs;" \
409 "tftp $loadaddr $bootfile;" \
410 "tftp $fdtaddr $fdtfile;" \
411 "bootm $loadaddr - $fdtaddr"
413 #define CONFIG_RAMBOOTCOMMAND \
414 "setenv rootdev /dev/ram;" \
416 "tftp $ramdiskaddr $ramdiskfile;" \
417 "tftp $loadaddr $bootfile;" \
418 "tftp $fdtaddr $fdtfile;" \
419 "bootm $loadaddr $ramdiskaddr $fdtaddr"
421 #endif /* __CONFIG_H */