1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
6 * mpc8313epb board configuration file
13 * High Level Configuration Options
16 #define CONFIG_MPC8313ERDB 1
18 #define CONFIG_SPL_INIT_MINIMAL
19 #define CONFIG_SPL_FLUSH_IMAGE
20 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
21 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
23 #ifdef CONFIG_SPL_BUILD
24 #define CONFIG_NS16550_MIN_FUNCTIONS
27 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
28 #define CONFIG_SPL_MAX_SIZE (4 * 1024)
29 #define CONFIG_SPL_PAD_TO 0x4000
31 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
32 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
33 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
34 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
35 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
36 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
38 #ifdef CONFIG_SPL_BUILD
39 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
42 #ifndef CONFIG_SYS_MONITOR_BASE
43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
46 #define CONFIG_PCI_INDIRECT_BRIDGE
47 #define CONFIG_FSL_ELBC 1
55 #define CONFIG_VSC7385_ENET
58 #ifdef CONFIG_SYS_66MHZ
59 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
60 #elif defined(CONFIG_SYS_33MHZ)
61 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
63 #error Unknown oscillator frequency.
66 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
68 #define CONFIG_SYS_IMMR 0xE0000000
70 #if !defined(CONFIG_SPL_BUILD)
71 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
74 #define CONFIG_SYS_MEMTEST_START 0x00001000
75 #define CONFIG_SYS_MEMTEST_END 0x07f00000
77 /* Early revs of this board will lock up hard when attempting
78 * to access the PMC registers, unless a JTAG debugger is
79 * connected, or some resistor modifications are made.
81 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
83 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
84 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
87 * Device configurations
92 #ifdef CONFIG_VSC7385_ENET
96 /* The flash address and size of the VSC7385 firmware image */
97 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
98 #define CONFIG_VSC7385_IMAGE_SIZE 8192
105 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
107 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
110 * Manually set up DDR parameters, as this board does not
111 * seem to have the SPD connected to I2C.
113 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
114 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
115 | CSCONFIG_ODT_RD_NEVER \
116 | CSCONFIG_ODT_WR_ONLY_CURRENT \
117 | CSCONFIG_ROW_BIT_13 \
118 | CSCONFIG_COL_BIT_10)
121 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
122 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
123 | (0 << TIMING_CFG0_WRT_SHIFT) \
124 | (0 << TIMING_CFG0_RRT_SHIFT) \
125 | (0 << TIMING_CFG0_WWT_SHIFT) \
126 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
127 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
128 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
129 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
131 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
132 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
133 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
134 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
135 | (10 << TIMING_CFG1_REFREC_SHIFT) \
136 | (3 << TIMING_CFG1_WRREC_SHIFT) \
137 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
138 | (2 << TIMING_CFG1_WRTORD_SHIFT))
140 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
141 | (5 << TIMING_CFG2_CPO_SHIFT) \
142 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
143 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
144 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
145 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
146 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
147 /* 0x129048c6 */ /* P9-45,may need tuning */
148 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
149 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
151 #if defined(CONFIG_DDR_2T_TIMING)
152 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
153 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
158 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
159 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
163 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
164 /* set burst length to 8 for 32-bit data path */
165 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
166 | (0x0632 << SDRAM_MODE_SD_SHIFT))
168 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
170 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
172 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
178 * FLASH on the Local Bus
180 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
181 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
182 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
184 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE \
185 | BR_PS_16 /* 16 bit port */ \
186 | BR_MS_GPCM /* MSEL = GPCM */ \
188 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
193 /* 0xFF006FF7 TODO SLOW 16 MB flash size */
194 /* window base at flash base */
195 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
196 /* 16 MB window size */
197 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
199 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
200 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
202 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
203 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
205 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
206 !defined(CONFIG_SPL_BUILD)
207 #define CONFIG_SYS_RAMBOOT
210 #define CONFIG_SYS_INIT_RAM_LOCK 1
211 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
212 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
214 #define CONFIG_SYS_GBL_DATA_OFFSET \
215 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
216 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
218 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
219 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
220 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
223 * Local Bus LCRR and LBCR regs
225 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
226 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
227 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
228 | (0xFF << LBCR_BMT_SHIFT) \
229 | 0xF) /* 0x0004ff0f */
231 /* LB refresh timer prescal, 266MHz/32 */
232 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
234 /* drivers/mtd/nand/raw/nand.c */
235 #if defined(CONFIG_SPL_BUILD)
236 #define CONFIG_SYS_NAND_BASE 0xFFF00000
238 #define CONFIG_SYS_NAND_BASE 0xE2800000
241 #define CONFIG_MTD_PARTITION
243 #define CONFIG_SYS_MAX_NAND_DEVICE 1
244 #define CONFIG_NAND_FSL_ELBC 1
245 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
246 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
248 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_NAND_BASE \
249 | BR_DECC_CHK_GEN /* Use HW ECC */ \
250 | BR_PS_8 /* 8 bit port */ \
251 | BR_MS_FCM /* MSEL = FCM */ \
253 #define CONFIG_SYS_OR0_PRELIM \
254 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
263 /* Still needed for spl_minimal.c */
264 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
265 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
267 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
268 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
270 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
271 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
273 /* local bus write LED / read status buffer (BCSR) mapping */
274 #define CONFIG_SYS_BCSR_ADDR 0xFA000000
275 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
276 /* map at 0xFA000000 on LCS3 */
277 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
278 | BR_PS_8 /* 8 bit port */ \
279 | BR_MS_GPCM /* MSEL = GPCM */ \
282 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
291 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
292 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
296 #ifdef CONFIG_VSC7385_ENET
298 /* VSC7385 Base address on LCS2 */
299 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
300 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
302 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
303 | BR_PS_8 /* 8 bit port */ \
304 | BR_MS_GPCM /* MSEL = GPCM */ \
306 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
316 /* Access window base at VSC7385 base */
317 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
318 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
322 #define CONFIG_MPC83XX_GPIO 1
327 #define CONFIG_SYS_NS16550_SERIAL
328 #define CONFIG_SYS_NS16550_REG_SIZE 1
330 #define CONFIG_SYS_BAUDRATE_TABLE \
331 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
333 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
334 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
337 #define CONFIG_SYS_I2C
338 #define CONFIG_SYS_I2C_FSL
339 #define CONFIG_SYS_FSL_I2C_SPEED 400000
340 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
341 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
342 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
343 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
344 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
345 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
349 * Addresses are mapped 1-1.
351 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
352 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
353 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
354 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
355 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
356 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
357 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
358 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
359 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
361 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
367 #define CONFIG_GMII /* MII PHY management */
370 #define CONFIG_HAS_ETH0
371 #define CONFIG_TSEC1_NAME "TSEC0"
372 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
373 #define TSEC1_PHY_ADDR 0x1c
374 #define TSEC1_FLAGS TSEC_GIGABIT
375 #define TSEC1_PHYIDX 0
379 #define CONFIG_HAS_ETH1
380 #define CONFIG_TSEC2_NAME "TSEC1"
381 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
382 #define TSEC2_PHY_ADDR 4
383 #define TSEC2_FLAGS TSEC_GIGABIT
384 #define TSEC2_PHYIDX 0
387 /* Options are: TSEC[0-1] */
388 #define CONFIG_ETHPRIME "TSEC1"
391 * Configure on-board RTC
393 #define CONFIG_RTC_DS1337
394 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
399 #define CONFIG_ENV_OFFSET (512 * 1024)
400 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
401 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
402 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
403 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
404 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
406 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
407 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
412 #define CONFIG_BOOTP_BOOTFILESIZE
415 * Command line configuration.
419 * Miscellaneous configurable options
421 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
422 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
424 /* Boot Argument Buffer Size */
425 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
428 * For booting Linux, the board info and command line data
429 * have to be in the first 256 MB of memory, since this is
430 * the maximum mapped by the Linux kernel during initialization.
432 /* Initial Memory map for Linux*/
433 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
434 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
436 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
438 #ifdef CONFIG_SYS_66MHZ
440 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
442 #define CONFIG_SYS_HRCW_LOW (\
443 0x20000000 /* reserved, must be set */ |\
445 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
446 HRCWL_DDR_TO_SCB_CLK_2X1 |\
447 HRCWL_CSB_TO_CLKIN_2X1 |\
448 HRCWL_CORE_TO_CSB_2X1)
450 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
452 #elif defined(CONFIG_SYS_33MHZ)
454 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
456 #define CONFIG_SYS_HRCW_LOW (\
457 0x20000000 /* reserved, must be set */ |\
459 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
460 HRCWL_DDR_TO_SCB_CLK_2X1 |\
461 HRCWL_CSB_TO_CLKIN_5X1 |\
462 HRCWL_CORE_TO_CSB_2X1)
464 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
468 #define CONFIG_SYS_HRCW_HIGH_BASE (\
470 HRCWH_PCI1_ARBITER_ENABLE |\
472 HRCWH_BOOTSEQ_DISABLE |\
473 HRCWH_SW_WATCHDOG_DISABLE |\
474 HRCWH_TSEC1M_IN_RGMII |\
475 HRCWH_TSEC2M_IN_RGMII |\
478 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
479 HRCWH_FROM_0XFFF00100 |\
480 HRCWH_ROM_LOC_NAND_SP_8BIT |\
483 /* System IO Config */
484 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
485 /* Enable Internal USB Phy and GPIO on LCD Connector */
486 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
488 #define CONFIG_SYS_HID0_INIT 0x000000000
489 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
490 HID0_ENABLE_INSTRUCTION_CACHE | \
491 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
493 #define CONFIG_SYS_HID2 HID2_HBE
495 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
497 /* DDR @ 0x00000000 */
498 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
499 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
504 /* PCI @ 0x80000000 */
505 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
506 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
510 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
512 | BATL_CACHEINHIBIT \
513 | BATL_GUARDEDSTORAGE)
514 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
519 /* PCI2 not supported on 8313 */
520 #define CONFIG_SYS_IBAT3L (0)
521 #define CONFIG_SYS_IBAT3U (0)
522 #define CONFIG_SYS_IBAT4L (0)
523 #define CONFIG_SYS_IBAT4U (0)
525 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
526 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
528 | BATL_CACHEINHIBIT \
529 | BATL_GUARDEDSTORAGE)
530 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
535 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
536 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
537 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
539 #define CONFIG_SYS_IBAT7L (0)
540 #define CONFIG_SYS_IBAT7U (0)
542 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
543 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
544 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
545 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
546 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
547 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
548 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
549 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
550 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
551 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
552 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
553 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
554 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
555 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
556 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
557 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
560 * Environment Configuration
562 #define CONFIG_ENV_OVERWRITE
564 #define CONFIG_NETDEV "eth1"
566 #define CONFIG_HOSTNAME "mpc8313erdb"
567 #define CONFIG_ROOTPATH "/nfs/root/path"
568 #define CONFIG_BOOTFILE "uImage"
569 /* U-Boot image on TFTP server */
570 #define CONFIG_UBOOTPATH "u-boot.bin"
571 #define CONFIG_FDTFILE "mpc8313erdb.dtb"
573 /* default location for tftp and bootm */
574 #define CONFIG_LOADADDR 800000
576 #define CONFIG_EXTRA_ENV_SETTINGS \
577 "netdev=" CONFIG_NETDEV "\0" \
579 "uboot=" CONFIG_UBOOTPATH "\0" \
580 "tftpflash=tftpboot $loadaddr $uboot; " \
581 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
583 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
585 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
587 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
589 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
592 "fdtfile=" CONFIG_FDTFILE "\0" \
594 "setbootargs=setenv bootargs " \
595 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
596 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
597 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
599 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
601 #define CONFIG_NFSBOOTCOMMAND \
602 "setenv rootdev /dev/nfs;" \
605 "tftp $loadaddr $bootfile;" \
606 "tftp $fdtaddr $fdtfile;" \
607 "bootm $loadaddr - $fdtaddr"
609 #define CONFIG_RAMBOOTCOMMAND \
610 "setenv rootdev /dev/ram;" \
612 "tftp $ramdiskaddr $ramdiskfile;" \
613 "tftp $loadaddr $bootfile;" \
614 "tftp $fdtaddr $fdtfile;" \
615 "bootm $loadaddr $ramdiskaddr $fdtaddr"
617 #endif /* __CONFIG_H */