include/configs/MPC8313ERDB_NAND.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   4  */
   5 /*
   6  * mpc8313epb board configuration file
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1
  16
  17 #define CONFIG_SPL_INIT_MINIMAL
  18 #define CONFIG_SPL_FLUSH_IMAGE
  19 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  20 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
  21
  22 #ifdef CONFIG_SPL_BUILD
  23 #define CONFIG_NS16550_MIN_FUNCTIONS
  24 #endif
  25
  26 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  27 #define CONFIG_SPL_MAX_SIZE     (4 * 1024)
  28 #define CONFIG_SPL_PAD_TO       0x4000
  29
  30 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  31 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  32 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  33 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  34 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  35 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  36
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  39 #endif
  40
  41 #ifndef CONFIG_SYS_MONITOR_BASE
  42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  43 #endif
  44
  45 #define CONFIG_PCI_INDIRECT_BRIDGE
  46
  47 /*
  48  * On-board devices
  49  *
  50  * TSEC1 is VSC switch
  51  * TSEC2 is SoC TSEC
  52  */
  53 #define CONFIG_VSC7385_ENET
  54 #define CONFIG_TSEC2
  55
  56 #if !defined(CONFIG_SPL_BUILD)
  57 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
  58 #endif
  59
  60 #define CONFIG_SYS_MEMTEST_START        0x00001000
  61 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  62
  63 /* Early revs of this board will lock up hard when attempting
  64  * to access the PMC registers, unless a JTAG debugger is
  65  * connected, or some resistor modifications are made.
  66  */
  67 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  68
  69 /*
  70  * Device configurations
  71  */
  72
  73 /* Vitesse 7385 */
  74
  75 #ifdef CONFIG_VSC7385_ENET
  76
  77 #define CONFIG_TSEC1
  78
  79 /* The flash address and size of the VSC7385 firmware image */
  80 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  81 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  82
  83 #endif
  84
  85 /*
  86  * DDR Setup
  87  */
  88 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory*/
  89
  90 /*
  91  * Manually set up DDR parameters, as this board does not
  92  * seem to have the SPD connected to I2C.
  93  */
  94 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
  95 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  96                                 | CSCONFIG_ODT_RD_NEVER \
  97                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  98                                 | CSCONFIG_ROW_BIT_13 \
  99                                 | CSCONFIG_COL_BIT_10)
 100                                 /* 0x80010102 */
 101
 102 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 103 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 104                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 105                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 106                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 107                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 108                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 109                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 110                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 111                                 /* 0x00220802 */
 112 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 113                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 114                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 115                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 116                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
 117                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 118                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 119                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 120                                 /* 0x3835a322 */
 121 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 122                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 123                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 124                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 125                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 126                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 127                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 128                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 129 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 130                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 131                                 /* 0x05100500 */
 132 #if defined(CONFIG_DDR_2T_TIMING)
 133 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 134                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 135                                 | SDRAM_CFG_DBW_32 \
 136                                 | SDRAM_CFG_2T_EN)
 137                                 /* 0x43088000 */
 138 #else
 139 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 140                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 141                                 | SDRAM_CFG_DBW_32)
 142                                 /* 0x43080000 */
 143 #endif
 144 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 145 /* set burst length to 8 for 32-bit data path */
 146 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 147                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 148                                 /* 0x44480632 */
 149 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 150
 151 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 152                                 /*0x02000000*/
 153 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 154                                 | DDRCDR_PZ_NOMZ \
 155                                 | DDRCDR_NZ_NOMZ \
 156                                 | DDRCDR_M_ODR)
 157
 158 /*
 159  * FLASH on the Local Bus
 160  */
 161 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 162 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 163 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 164
 165 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 166 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 167
 168 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 169 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 170
 171 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 172         !defined(CONFIG_SPL_BUILD)
 173 #define CONFIG_SYS_RAMBOOT
 174 #endif
 175
 176 #define CONFIG_SYS_INIT_RAM_LOCK        1
 177 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 178 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 179
 180 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 181                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 182 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 183
 184 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 185 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 186 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 187
 188 /* drivers/mtd/nand/raw/nand.c */
 189 #if defined(CONFIG_SPL_BUILD)
 190 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 191 #else
 192 #define CONFIG_SYS_NAND_BASE            0xE2800000
 193 #endif
 194
 195 #define CONFIG_MTD_PARTITION
 196
 197 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 198 #define CONFIG_NAND_FSL_ELBC 1
 199 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 200 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 201
 202 /* Still needed for spl_minimal.c */
 203 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
 204 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
 205
 206 /* local bus write LED / read status buffer (BCSR) mapping */
 207 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 208 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 209                                         /* map at 0xFA000000 on LCS3 */
 210
 211 /* Vitesse 7385 */
 212
 213 #ifdef CONFIG_VSC7385_ENET
 214
 215                                         /* VSC7385 Base address on LCS2 */
 216 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 217 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 218
 219
 220 #endif
 221
 222 #define CONFIG_MPC83XX_GPIO 1
 223
 224 /*
 225  * Serial Port
 226  */
 227 #define CONFIG_SYS_NS16550_SERIAL
 228 #define CONFIG_SYS_NS16550_REG_SIZE     1
 229
 230 #define CONFIG_SYS_BAUDRATE_TABLE       \
 231         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 232
 233 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 234 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 235
 236 /* I2C */
 237 #define CONFIG_SYS_I2C
 238 #define CONFIG_SYS_I2C_FSL
 239 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 240 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 241 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 242 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 243 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 244 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 245 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 246
 247 /*
 248  * General PCI
 249  * Addresses are mapped 1-1.
 250  */
 251 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 252 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 253 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 254 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 255 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 256 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 257 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 258 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 259 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 260
 261 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 262
 263 /*
 264  * TSEC
 265  */
 266
 267 #define CONFIG_GMII                     /* MII PHY management */
 268
 269 #ifdef CONFIG_TSEC1
 270 #define CONFIG_HAS_ETH0
 271 #define CONFIG_TSEC1_NAME       "TSEC0"
 272 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 273 #define TSEC1_PHY_ADDR          0x1c
 274 #define TSEC1_FLAGS             TSEC_GIGABIT
 275 #define TSEC1_PHYIDX            0
 276 #endif
 277
 278 #ifdef CONFIG_TSEC2
 279 #define CONFIG_HAS_ETH1
 280 #define CONFIG_TSEC2_NAME       "TSEC1"
 281 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 282 #define TSEC2_PHY_ADDR          4
 283 #define TSEC2_FLAGS             TSEC_GIGABIT
 284 #define TSEC2_PHYIDX            0
 285 #endif
 286
 287 /* Options are: TSEC[0-1] */
 288 #define CONFIG_ETHPRIME                 "TSEC1"
 289
 290 /*
 291  * Configure on-board RTC
 292  */
 293 #define CONFIG_RTC_DS1337
 294 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 295
 296 /*
 297  * Environment
 298  */
 299 #define CONFIG_ENV_RANGE                (CONFIG_SYS_NAND_BLOCK_SIZE * 4)
 300
 301 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 302 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 303
 304 /*
 305  * BOOTP options
 306  */
 307 #define CONFIG_BOOTP_BOOTFILESIZE
 308
 309 /*
 310  * Command line configuration.
 311  */
 312
 313 /*
 314  * Miscellaneous configurable options
 315  */
 316 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 317 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 318
 319                                 /* Boot Argument Buffer Size */
 320 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 321
 322 /*
 323  * For booting Linux, the board info and command line data
 324  * have to be in the first 256 MB of memory, since this is
 325  * the maximum mapped by the Linux kernel during initialization.
 326  */
 327                                 /* Initial Memory map for Linux*/
 328 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 329 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 330
 331 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 332
 333 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
 334
 335 /* System IO Config */
 336 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 337                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 338 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 339
 340 /*
 341  * Environment Configuration
 342  */
 343 #define CONFIG_ENV_OVERWRITE
 344
 345 #define CONFIG_NETDEV           "eth1"
 346
 347 #define CONFIG_HOSTNAME         "mpc8313erdb"
 348 #define CONFIG_ROOTPATH         "/nfs/root/path"
 349 #define CONFIG_BOOTFILE         "uImage"
 350                                 /* U-Boot image on TFTP server */
 351 #define CONFIG_UBOOTPATH        "u-boot.bin"
 352 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 353
 354                                 /* default location for tftp and bootm */
 355 #define CONFIG_LOADADDR         800000
 356
 357 #define CONFIG_EXTRA_ENV_SETTINGS \
 358         "netdev=" CONFIG_NETDEV "\0"                                    \
 359         "ethprime=TSEC1\0"                                              \
 360         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 361         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 362                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 363                         " +$filesize; " \
 364                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 365                         " +$filesize; " \
 366                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 367                         " $filesize; "  \
 368                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 369                         " +$filesize; " \
 370                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 371                         " $filesize\0"  \
 372         "fdtaddr=780000\0"                                              \
 373         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 374         "console=ttyS0\0"                                               \
 375         "setbootargs=setenv bootargs "                                  \
 376                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 377         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 378                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 379                                                         "$netdev:off " \
 380                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 381
 382 #define CONFIG_NFSBOOTCOMMAND                                           \
 383         "setenv rootdev /dev/nfs;"                                      \
 384         "run setbootargs;"                                              \
 385         "run setipargs;"                                                \
 386         "tftp $loadaddr $bootfile;"                                     \
 387         "tftp $fdtaddr $fdtfile;"                                       \
 388         "bootm $loadaddr - $fdtaddr"
 389
 390 #define CONFIG_RAMBOOTCOMMAND                                           \
 391         "setenv rootdev /dev/ram;"                                      \
 392         "run setbootargs;"                                              \
 393         "tftp $ramdiskaddr $ramdiskfile;"                               \
 394         "tftp $loadaddr $bootfile;"                                     \
 395         "tftp $fdtaddr $fdtfile;"                                       \
 396         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 397
 398 #endif  /* __CONFIG_H */