1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
6 * mpc8313epb board configuration file
12 #include <linux/stringify.h>
15 * High Level Configuration Options
19 #define CONFIG_SPL_INIT_MINIMAL
20 #define CONFIG_SPL_FLUSH_IMAGE
21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
22 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
24 #ifdef CONFIG_SPL_BUILD
25 #define CONFIG_NS16550_MIN_FUNCTIONS
28 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
29 #define CONFIG_SPL_MAX_SIZE (4 * 1024)
30 #define CONFIG_SPL_PAD_TO 0x4000
32 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
33 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
34 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
35 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
36 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
37 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
39 #ifdef CONFIG_SPL_BUILD
40 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
43 #ifndef CONFIG_SYS_MONITOR_BASE
44 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
47 #define CONFIG_PCI_INDIRECT_BRIDGE
55 #define CONFIG_VSC7385_ENET
58 #if !defined(CONFIG_SPL_BUILD)
59 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
62 /* Early revs of this board will lock up hard when attempting
63 * to access the PMC registers, unless a JTAG debugger is
64 * connected, or some resistor modifications are made.
66 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
69 * Device configurations
74 #ifdef CONFIG_VSC7385_ENET
78 /* The flash address and size of the VSC7385 firmware image */
79 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
80 #define CONFIG_VSC7385_IMAGE_SIZE 8192
87 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
90 * Manually set up DDR parameters, as this board does not
91 * seem to have the SPD connected to I2C.
93 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
94 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
95 | CSCONFIG_ODT_RD_NEVER \
96 | CSCONFIG_ODT_WR_ONLY_CURRENT \
97 | CSCONFIG_ROW_BIT_13 \
98 | CSCONFIG_COL_BIT_10)
101 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
102 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
103 | (0 << TIMING_CFG0_WRT_SHIFT) \
104 | (0 << TIMING_CFG0_RRT_SHIFT) \
105 | (0 << TIMING_CFG0_WWT_SHIFT) \
106 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
107 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
108 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
109 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
111 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
112 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
113 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
114 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
115 | (10 << TIMING_CFG1_REFREC_SHIFT) \
116 | (3 << TIMING_CFG1_WRREC_SHIFT) \
117 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
118 | (2 << TIMING_CFG1_WRTORD_SHIFT))
120 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
121 | (5 << TIMING_CFG2_CPO_SHIFT) \
122 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
123 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
124 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
125 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
126 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
127 /* 0x129048c6 */ /* P9-45,may need tuning */
128 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
129 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
131 #if defined(CONFIG_DDR_2T_TIMING)
132 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
133 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
138 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
139 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
143 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
144 /* set burst length to 8 for 32-bit data path */
145 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
146 | (0x0632 << SDRAM_MODE_SD_SHIFT))
148 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
150 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
152 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
158 * FLASH on the Local Bus
160 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
161 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
162 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
164 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
165 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
167 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
168 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
170 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
171 !defined(CONFIG_SPL_BUILD)
172 #define CONFIG_SYS_RAMBOOT
175 #define CONFIG_SYS_INIT_RAM_LOCK 1
176 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
177 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
179 #define CONFIG_SYS_GBL_DATA_OFFSET \
180 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
181 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
183 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
184 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
185 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
187 /* drivers/mtd/nand/raw/nand.c */
188 #if defined(CONFIG_SPL_BUILD)
189 #define CONFIG_SYS_NAND_BASE 0xFFF00000
191 #define CONFIG_SYS_NAND_BASE 0xE2800000
194 #define CONFIG_MTD_PARTITION
196 #define CONFIG_SYS_MAX_NAND_DEVICE 1
197 #define CONFIG_NAND_FSL_ELBC 1
198 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
199 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
201 /* Still needed for spl_minimal.c */
202 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
203 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
205 /* local bus write LED / read status buffer (BCSR) mapping */
206 #define CONFIG_SYS_BCSR_ADDR 0xFA000000
207 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
208 /* map at 0xFA000000 on LCS3 */
212 #ifdef CONFIG_VSC7385_ENET
214 /* VSC7385 Base address on LCS2 */
215 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
216 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
221 #define CONFIG_MPC83XX_GPIO 1
226 #define CONFIG_SYS_NS16550_SERIAL
227 #define CONFIG_SYS_NS16550_REG_SIZE 1
229 #define CONFIG_SYS_BAUDRATE_TABLE \
230 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
232 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
233 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
236 #define CONFIG_SYS_I2C
237 #define CONFIG_SYS_I2C_FSL
238 #define CONFIG_SYS_FSL_I2C_SPEED 400000
239 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
240 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
241 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
242 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
243 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
244 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
248 * Addresses are mapped 1-1.
250 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
251 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
252 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
253 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
254 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
255 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
256 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
257 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
258 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
260 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
266 #define CONFIG_GMII /* MII PHY management */
269 #define CONFIG_HAS_ETH0
270 #define CONFIG_TSEC1_NAME "TSEC0"
271 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
272 #define TSEC1_PHY_ADDR 0x1c
273 #define TSEC1_FLAGS TSEC_GIGABIT
274 #define TSEC1_PHYIDX 0
278 #define CONFIG_HAS_ETH1
279 #define CONFIG_TSEC2_NAME "TSEC1"
280 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
281 #define TSEC2_PHY_ADDR 4
282 #define TSEC2_FLAGS TSEC_GIGABIT
283 #define TSEC2_PHYIDX 0
286 /* Options are: TSEC[0-1] */
287 #define CONFIG_ETHPRIME "TSEC1"
290 * Configure on-board RTC
292 #define CONFIG_RTC_DS1337
293 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
298 #define CONFIG_ENV_RANGE (CONFIG_SYS_NAND_BLOCK_SIZE * 4)
300 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
301 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
306 #define CONFIG_BOOTP_BOOTFILESIZE
309 * Miscellaneous configurable options
311 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
312 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
314 /* Boot Argument Buffer Size */
315 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
318 * For booting Linux, the board info and command line data
319 * have to be in the first 256 MB of memory, since this is
320 * the maximum mapped by the Linux kernel during initialization.
322 /* Initial Memory map for Linux*/
323 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
324 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
326 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
328 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
330 /* System IO Config */
331 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
332 /* Enable Internal USB Phy and GPIO on LCD Connector */
333 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
336 * Environment Configuration
338 #define CONFIG_ENV_OVERWRITE
340 #define CONFIG_NETDEV "eth1"
342 #define CONFIG_HOSTNAME "mpc8313erdb"
343 #define CONFIG_ROOTPATH "/nfs/root/path"
344 #define CONFIG_BOOTFILE "uImage"
345 /* U-Boot image on TFTP server */
346 #define CONFIG_UBOOTPATH "u-boot.bin"
347 #define CONFIG_FDTFILE "mpc8313erdb.dtb"
349 /* default location for tftp and bootm */
350 #define CONFIG_LOADADDR 800000
352 #define CONFIG_EXTRA_ENV_SETTINGS \
353 "netdev=" CONFIG_NETDEV "\0" \
355 "uboot=" CONFIG_UBOOTPATH "\0" \
356 "tftpflash=tftpboot $loadaddr $uboot; " \
357 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
359 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
361 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
363 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
365 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
368 "fdtfile=" CONFIG_FDTFILE "\0" \
370 "setbootargs=setenv bootargs " \
371 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
372 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
373 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
375 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
377 #define CONFIG_NFSBOOTCOMMAND \
378 "setenv rootdev /dev/nfs;" \
381 "tftp $loadaddr $bootfile;" \
382 "tftp $fdtaddr $fdtfile;" \
383 "bootm $loadaddr - $fdtaddr"
385 #define CONFIG_RAMBOOTCOMMAND \
386 "setenv rootdev /dev/ram;" \
388 "tftp $ramdiskaddr $ramdiskfile;" \
389 "tftp $loadaddr $bootfile;" \
390 "tftp $fdtaddr $fdtfile;" \
391 "bootm $loadaddr $ramdiskaddr $fdtaddr"
393 #endif /* __CONFIG_H */