include/configs/MPC8313ERDB.h

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 /*
   7  * mpc8313epb board configuration file
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_DISPLAY_BOARDINFO
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_E300             1
  19 #define CONFIG_MPC831x          1
  20 #define CONFIG_MPC8313          1
  21 #define CONFIG_MPC8313ERDB      1
  22
  23 #ifdef CONFIG_NAND
  24 #define CONFIG_SPL_INIT_MINIMAL
  25 #define CONFIG_SPL_SERIAL_SUPPORT
  26 #define CONFIG_SPL_FLUSH_IMAGE
  27 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  28 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
  29
  30 #ifdef CONFIG_SPL_BUILD
  31 #define CONFIG_NS16550_MIN_FUNCTIONS
  32 #endif
  33
  34 #define CONFIG_SYS_TEXT_BASE    0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
  35 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  36 #define CONFIG_SPL_MAX_SIZE     (4 * 1024)
  37 #define CONFIG_SPL_PAD_TO       0x4000
  38
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  40 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  41 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  42 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  43 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  44 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  45
  46 #ifdef CONFIG_SPL_BUILD
  47 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  48 #endif
  49
  50 #endif /* CONFIG_NAND */
  51
  52 #ifndef CONFIG_SYS_TEXT_BASE
  53 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  54 #endif
  55
  56 #ifndef CONFIG_SYS_MONITOR_BASE
  57 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  58 #endif
  59
  60 #define CONFIG_PCI
  61 #define CONFIG_PCI_INDIRECT_BRIDGE
  62 #define CONFIG_FSL_ELBC 1
  63
  64 #define CONFIG_MISC_INIT_R
  65
  66 /*
  67  * On-board devices
  68  *
  69  * TSEC1 is VSC switch
  70  * TSEC2 is SoC TSEC
  71  */
  72 #define CONFIG_VSC7385_ENET
  73 #define CONFIG_TSEC2
  74
  75 #ifdef CONFIG_SYS_66MHZ
  76 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  77 #elif defined(CONFIG_SYS_33MHZ)
  78 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
  79 #else
  80 #error Unknown oscillator frequency.
  81 #endif
  82
  83 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  84
  85 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f */
  86 #define CONFIG_BOARD_EARLY_INIT_R               /* call board_early_init_r */
  87
  88 #define CONFIG_SYS_IMMR         0xE0000000
  89
  90 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
  91 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
  92 #endif
  93
  94 #define CONFIG_SYS_MEMTEST_START        0x00001000
  95 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  96
  97 /* Early revs of this board will lock up hard when attempting
  98  * to access the PMC registers, unless a JTAG debugger is
  99  * connected, or some resistor modifications are made.
 100  */
 101 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
 102
 103 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 104 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
 105
 106 /*
 107  * Device configurations
 108  */
 109
 110 /* Vitesse 7385 */
 111
 112 #ifdef CONFIG_VSC7385_ENET
 113
 114 #define CONFIG_TSEC1
 115
 116 /* The flash address and size of the VSC7385 firmware image */
 117 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 118 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 119
 120 #endif
 121
 122 /*
 123  * DDR Setup
 124  */
 125 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 126 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 127 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 128
 129 /*
 130  * Manually set up DDR parameters, as this board does not
 131  * seem to have the SPD connected to I2C.
 132  */
 133 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
 134 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 135                                 | CSCONFIG_ODT_RD_NEVER \
 136                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 137                                 | CSCONFIG_ROW_BIT_13 \
 138                                 | CSCONFIG_COL_BIT_10)
 139                                 /* 0x80010102 */
 140
 141 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 142 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 143                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 144                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 145                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 146                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 147                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 148                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 149                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 150                                 /* 0x00220802 */
 151 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 152                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 153                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 154                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 155                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
 156                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 157                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 158                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 159                                 /* 0x3835a322 */
 160 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 161                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 162                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 163                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 164                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 165                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 166                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 167                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 168 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 169                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 170                                 /* 0x05100500 */
 171 #if defined(CONFIG_DDR_2T_TIMING)
 172 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 173                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 174                                 | SDRAM_CFG_DBW_32 \
 175                                 | SDRAM_CFG_2T_EN)
 176                                 /* 0x43088000 */
 177 #else
 178 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 179                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 180                                 | SDRAM_CFG_DBW_32)
 181                                 /* 0x43080000 */
 182 #endif
 183 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 184 /* set burst length to 8 for 32-bit data path */
 185 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 186                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 187                                 /* 0x44480632 */
 188 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 189
 190 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 191                                 /*0x02000000*/
 192 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 193                                 | DDRCDR_PZ_NOMZ \
 194                                 | DDRCDR_NZ_NOMZ \
 195                                 | DDRCDR_M_ODR)
 196
 197 /*
 198  * FLASH on the Local Bus
 199  */
 200 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 201 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 202 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 203 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 204 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 205 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 206 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
 207
 208 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
 209                                         | BR_PS_16      /* 16 bit port */ \
 210                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 211                                         | BR_V)         /* valid */
 212 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 213                                 | OR_GPCM_XACS \
 214                                 | OR_GPCM_SCY_9 \
 215                                 | OR_GPCM_EHTR \
 216                                 | OR_GPCM_EAD)
 217                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
 218                                         /* window base at flash base */
 219 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 220                                         /* 16 MB window size */
 221 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 222
 223 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 224 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 225
 226 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 227 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 228
 229 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 230         !defined(CONFIG_SPL_BUILD)
 231 #define CONFIG_SYS_RAMBOOT
 232 #endif
 233
 234 #define CONFIG_SYS_INIT_RAM_LOCK        1
 235 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 236 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 237
 238 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 239                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 240 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 241
 242 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 243 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 244 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 245
 246 /*
 247  * Local Bus LCRR and LBCR regs
 248  */
 249 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 250 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 251 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 252                                 | (0xFF << LBCR_BMT_SHIFT) \
 253                                 | 0xF)  /* 0x0004ff0f */
 254
 255                                 /* LB refresh timer prescal, 266MHz/32 */
 256 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
 257
 258 /* drivers/mtd/nand/nand.c */
 259 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
 260 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 261 #else
 262 #define CONFIG_SYS_NAND_BASE            0xE2800000
 263 #endif
 264
 265 #define CONFIG_MTD_DEVICE
 266 #define CONFIG_MTD_PARTITION
 267 #define CONFIG_CMD_MTDPARTS
 268 #define MTDIDS_DEFAULT                  "nand0=e2800000.flash"
 269 #define MTDPARTS_DEFAULT                \
 270         "mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
 271
 272 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 273 #define CONFIG_CMD_NAND 1
 274 #define CONFIG_NAND_FSL_ELBC 1
 275 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 276 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 277
 278 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 279                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 280                                 | BR_PS_8               /* 8 bit port */ \
 281                                 | BR_MS_FCM             /* MSEL = FCM */ \
 282                                 | BR_V)                 /* valid */
 283 #define CONFIG_SYS_NAND_OR_PRELIM       \
 284                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 285                                 | OR_FCM_CSCT \
 286                                 | OR_FCM_CST \
 287                                 | OR_FCM_CHT \
 288                                 | OR_FCM_SCY_1 \
 289                                 | OR_FCM_TRLX \
 290                                 | OR_FCM_EHTR)
 291                                 /* 0xFFFF8396 */
 292
 293 #ifdef CONFIG_NAND
 294 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 295 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 296 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 297 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 298 #else
 299 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 300 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 301 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 302 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 303 #endif
 304
 305 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 306 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 307
 308 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 309 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 310
 311 /* local bus write LED / read status buffer (BCSR) mapping */
 312 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 313 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 314                                         /* map at 0xFA000000 on LCS3 */
 315 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_BCSR_ADDR \
 316                                         | BR_PS_8       /* 8 bit port */ \
 317                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 318                                         | BR_V)         /* valid */
 319                                         /* 0xFA000801 */
 320 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
 321                                         | OR_GPCM_CSNT \
 322                                         | OR_GPCM_ACS_DIV2 \
 323                                         | OR_GPCM_XACS \
 324                                         | OR_GPCM_SCY_15 \
 325                                         | OR_GPCM_TRLX_SET \
 326                                         | OR_GPCM_EHTR_SET \
 327                                         | OR_GPCM_EAD)
 328                                         /* 0xFFFF8FF7 */
 329 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_BCSR_ADDR
 330 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 331
 332 /* Vitesse 7385 */
 333
 334 #ifdef CONFIG_VSC7385_ENET
 335
 336                                         /* VSC7385 Base address on LCS2 */
 337 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 338 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 339
 340 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 341                                         | BR_PS_8       /* 8 bit port */ \
 342                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 343                                         | BR_V)         /* valid */
 344 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
 345                                         | OR_GPCM_CSNT \
 346                                         | OR_GPCM_XACS \
 347                                         | OR_GPCM_SCY_15 \
 348                                         | OR_GPCM_SETA \
 349                                         | OR_GPCM_TRLX_SET \
 350                                         | OR_GPCM_EHTR_SET \
 351                                         | OR_GPCM_EAD)
 352                                         /* 0xFFFE09FF */
 353
 354                                         /* Access window base at VSC7385 base */
 355 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 356 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 357
 358 #endif
 359
 360 #define CONFIG_MPC83XX_GPIO 1
 361
 362 /*
 363  * Serial Port
 364  */
 365 #define CONFIG_CONS_INDEX       1
 366 #define CONFIG_SYS_NS16550_SERIAL
 367 #define CONFIG_SYS_NS16550_REG_SIZE     1
 368
 369 #define CONFIG_SYS_BAUDRATE_TABLE       \
 370         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 371
 372 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 373 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 374
 375 /* I2C */
 376 #define CONFIG_SYS_I2C
 377 #define CONFIG_SYS_I2C_FSL
 378 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 379 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 380 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 381 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 382 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 383 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 384 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 385
 386 /*
 387  * General PCI
 388  * Addresses are mapped 1-1.
 389  */
 390 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 391 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 392 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 393 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 394 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 395 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 396 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 397 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 398 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 399
 400 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 401 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 402
 403 /*
 404  * TSEC
 405  */
 406 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 407
 408 #define CONFIG_GMII                     /* MII PHY management */
 409
 410 #ifdef CONFIG_TSEC1
 411 #define CONFIG_HAS_ETH0
 412 #define CONFIG_TSEC1_NAME       "TSEC0"
 413 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 414 #define TSEC1_PHY_ADDR          0x1c
 415 #define TSEC1_FLAGS             TSEC_GIGABIT
 416 #define TSEC1_PHYIDX            0
 417 #endif
 418
 419 #ifdef CONFIG_TSEC2
 420 #define CONFIG_HAS_ETH1
 421 #define CONFIG_TSEC2_NAME       "TSEC1"
 422 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 423 #define TSEC2_PHY_ADDR          4
 424 #define TSEC2_FLAGS             TSEC_GIGABIT
 425 #define TSEC2_PHYIDX            0
 426 #endif
 427
 428 /* Options are: TSEC[0-1] */
 429 #define CONFIG_ETHPRIME                 "TSEC1"
 430
 431 /*
 432  * Configure on-board RTC
 433  */
 434 #define CONFIG_RTC_DS1337
 435 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 436
 437 /*
 438  * Environment
 439  */
 440 #if defined(CONFIG_NAND)
 441         #define CONFIG_ENV_IS_IN_NAND   1
 442         #define CONFIG_ENV_OFFSET               (512 * 1024)
 443         #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
 444         #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 445         #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 446         #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
 447         #define CONFIG_ENV_OFFSET_REDUND        \
 448                                         (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 449 #elif !defined(CONFIG_SYS_RAMBOOT)
 450         #define CONFIG_ENV_IS_IN_FLASH  1
 451         #define CONFIG_ENV_ADDR         \
 452                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 453         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 454         #define CONFIG_ENV_SIZE         0x2000
 455
 456 /* Address and size of Redundant Environment Sector */
 457 #else
 458         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 459         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 460         #define CONFIG_ENV_SIZE         0x2000
 461 #endif
 462
 463 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 464 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 465
 466 /*
 467  * BOOTP options
 468  */
 469 #define CONFIG_BOOTP_BOOTFILESIZE
 470 #define CONFIG_BOOTP_BOOTPATH
 471 #define CONFIG_BOOTP_GATEWAY
 472 #define CONFIG_BOOTP_HOSTNAME
 473
 474 /*
 475  * Command line configuration.
 476  */
 477 #define CONFIG_CMD_DATE
 478 #define CONFIG_CMD_PCI
 479
 480 #define CONFIG_CMDLINE_EDITING 1
 481 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
 482
 483 /*
 484  * Miscellaneous configurable options
 485  */
 486 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 487 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 488 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 489
 490                                                 /* Print Buffer Size */
 491 #define CONFIG_SYS_PBSIZE       \
 492                         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 493 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 494                                 /* Boot Argument Buffer Size */
 495 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 496
 497 /*
 498  * For booting Linux, the board info and command line data
 499  * have to be in the first 256 MB of memory, since this is
 500  * the maximum mapped by the Linux kernel during initialization.
 501  */
 502                                 /* Initial Memory map for Linux*/
 503 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 504 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 505
 506 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 507
 508 #ifdef CONFIG_SYS_66MHZ
 509
 510 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
 511 /* 0x62040000 */
 512 #define CONFIG_SYS_HRCW_LOW (\
 513         0x20000000 /* reserved, must be set */ |\
 514         HRCWL_DDRCM |\
 515         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 516         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 517         HRCWL_CSB_TO_CLKIN_2X1 |\
 518         HRCWL_CORE_TO_CSB_2X1)
 519
 520 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
 521
 522 #elif defined(CONFIG_SYS_33MHZ)
 523
 524 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
 525 /* 0x65040000 */
 526 #define CONFIG_SYS_HRCW_LOW (\
 527         0x20000000 /* reserved, must be set */ |\
 528         HRCWL_DDRCM |\
 529         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 530         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 531         HRCWL_CSB_TO_CLKIN_5X1 |\
 532         HRCWL_CORE_TO_CSB_2X1)
 533
 534 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
 535
 536 #endif
 537
 538 #define CONFIG_SYS_HRCW_HIGH_BASE (\
 539         HRCWH_PCI_HOST |\
 540         HRCWH_PCI1_ARBITER_ENABLE |\
 541         HRCWH_CORE_ENABLE |\
 542         HRCWH_BOOTSEQ_DISABLE |\
 543         HRCWH_SW_WATCHDOG_DISABLE |\
 544         HRCWH_TSEC1M_IN_RGMII |\
 545         HRCWH_TSEC2M_IN_RGMII |\
 546         HRCWH_BIG_ENDIAN)
 547
 548 #ifdef CONFIG_NAND
 549 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 550                        HRCWH_FROM_0XFFF00100 |\
 551                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
 552                        HRCWH_RL_EXT_NAND)
 553 #else
 554 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 555                        HRCWH_FROM_0X00000100 |\
 556                        HRCWH_ROM_LOC_LOCAL_16BIT |\
 557                        HRCWH_RL_EXT_LEGACY)
 558 #endif
 559
 560 /* System IO Config */
 561 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 562                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 563 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 564
 565 #define CONFIG_SYS_HID0_INIT    0x000000000
 566 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 567                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 568                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 569
 570 #define CONFIG_SYS_HID2 HID2_HBE
 571
 572 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 573
 574 /* DDR @ 0x00000000 */
 575 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 576 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 577                                 | BATU_BL_256M \
 578                                 | BATU_VS \
 579                                 | BATU_VP)
 580
 581 /* PCI @ 0x80000000 */
 582 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 583 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 584                                 | BATU_BL_256M \
 585                                 | BATU_VS \
 586                                 | BATU_VP)
 587 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 588                                 | BATL_PP_RW \
 589                                 | BATL_CACHEINHIBIT \
 590                                 | BATL_GUARDEDSTORAGE)
 591 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 592                                 | BATU_BL_256M \
 593                                 | BATU_VS \
 594                                 | BATU_VP)
 595
 596 /* PCI2 not supported on 8313 */
 597 #define CONFIG_SYS_IBAT3L       (0)
 598 #define CONFIG_SYS_IBAT3U       (0)
 599 #define CONFIG_SYS_IBAT4L       (0)
 600 #define CONFIG_SYS_IBAT4U       (0)
 601
 602 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 603 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 604                                 | BATL_PP_RW \
 605                                 | BATL_CACHEINHIBIT \
 606                                 | BATL_GUARDEDSTORAGE)
 607 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 608                                 | BATU_BL_256M \
 609                                 | BATU_VS \
 610                                 | BATU_VP)
 611
 612 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 613 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 614 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 615
 616 #define CONFIG_SYS_IBAT7L       (0)
 617 #define CONFIG_SYS_IBAT7U       (0)
 618
 619 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 620 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 621 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 622 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 623 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 624 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 625 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 626 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 627 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 628 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 629 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 630 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 631 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 632 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 633 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 634 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 635
 636 /*
 637  * Environment Configuration
 638  */
 639 #define CONFIG_ENV_OVERWRITE
 640
 641 #define CONFIG_NETDEV           "eth1"
 642
 643 #define CONFIG_HOSTNAME         mpc8313erdb
 644 #define CONFIG_ROOTPATH         "/nfs/root/path"
 645 #define CONFIG_BOOTFILE         "uImage"
 646                                 /* U-Boot image on TFTP server */
 647 #define CONFIG_UBOOTPATH        "u-boot.bin"
 648 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 649
 650                                 /* default location for tftp and bootm */
 651 #define CONFIG_LOADADDR         800000
 652 #define CONFIG_BAUDRATE         115200
 653
 654 #define CONFIG_EXTRA_ENV_SETTINGS \
 655         "netdev=" CONFIG_NETDEV "\0"                                    \
 656         "ethprime=TSEC1\0"                                              \
 657         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 658         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 659                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 660                         " +$filesize; " \
 661                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 662                         " +$filesize; " \
 663                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 664                         " $filesize; "  \
 665                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 666                         " +$filesize; " \
 667                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 668                         " $filesize\0"  \
 669         "fdtaddr=780000\0"                                              \
 670         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 671         "console=ttyS0\0"                                               \
 672         "setbootargs=setenv bootargs "                                  \
 673                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 674         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 675                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 676                                                         "$netdev:off " \
 677                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 678
 679 #define CONFIG_NFSBOOTCOMMAND                                           \
 680         "setenv rootdev /dev/nfs;"                                      \
 681         "run setbootargs;"                                              \
 682         "run setipargs;"                                                \
 683         "tftp $loadaddr $bootfile;"                                     \
 684         "tftp $fdtaddr $fdtfile;"                                       \
 685         "bootm $loadaddr - $fdtaddr"
 686
 687 #define CONFIG_RAMBOOTCOMMAND                                           \
 688         "setenv rootdev /dev/ram;"                                      \
 689         "run setbootargs;"                                              \
 690         "tftp $ramdiskaddr $ramdiskfile;"                               \
 691         "tftp $loadaddr $bootfile;"                                     \
 692         "tftp $fdtaddr $fdtfile;"                                       \
 693         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 694
 695 #endif  /* __CONFIG_H */