Makefile: Change CONFIG_SPL_PAD_TO to image offset
[platform/kernel/u-boot.git] / include / configs / MPC8313ERDB.h
1 /*
2  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 /*
23  * mpc8313epb board configuration file
24  */
25
26 #ifndef __CONFIG_H
27 #define __CONFIG_H
28
29 /*
30  * High Level Configuration Options
31  */
32 #define CONFIG_E300             1
33 #define CONFIG_MPC83xx          1
34 #define CONFIG_MPC831x          1
35 #define CONFIG_MPC8313          1
36 #define CONFIG_MPC8313ERDB      1
37
38 #ifdef CONFIG_NAND
39 #define CONFIG_SPL
40 #define CONFIG_SPL_INIT_MINIMAL
41 #define CONFIG_SPL_SERIAL_SUPPORT
42 #define CONFIG_SPL_NAND_SUPPORT
43 #define CONFIG_SPL_NAND_MINIMAL
44 #define CONFIG_SPL_FLUSH_IMAGE
45 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
46 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
47
48 #ifdef CONFIG_SPL_BUILD
49 #define CONFIG_NS16550_MIN_FUNCTIONS
50 #endif
51
52 #define CONFIG_SYS_TEXT_BASE    0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
53 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
54 #define CONFIG_SPL_MAX_SIZE     (4 * 1024)
55 #define CONFIG_SPL_PAD_TO       0x4000
56
57 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
58 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
59 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
60 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
61 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
62 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
63
64 #ifdef CONFIG_SPL_BUILD
65 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
66 #endif
67
68 #endif /* CONFIG_NAND */
69
70 #ifndef CONFIG_SYS_TEXT_BASE
71 #define CONFIG_SYS_TEXT_BASE    0xFE000000
72 #endif
73
74 #ifndef CONFIG_SYS_MONITOR_BASE
75 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
76 #endif
77
78 #define CONFIG_PCI
79 #define CONFIG_FSL_ELBC 1
80
81 #define CONFIG_MISC_INIT_R
82
83 /*
84  * On-board devices
85  *
86  * TSEC1 is VSC switch
87  * TSEC2 is SoC TSEC
88  */
89 #define CONFIG_VSC7385_ENET
90 #define CONFIG_TSEC2
91
92 #ifdef CONFIG_SYS_66MHZ
93 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
94 #elif defined(CONFIG_SYS_33MHZ)
95 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
96 #else
97 #error Unknown oscillator frequency.
98 #endif
99
100 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
101
102 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f */
103 #define CONFIG_BOARD_EARLY_INIT_R               /* call board_early_init_r */
104
105 #define CONFIG_SYS_IMMR         0xE0000000
106
107 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
108 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
109 #endif
110
111 #define CONFIG_SYS_MEMTEST_START        0x00001000
112 #define CONFIG_SYS_MEMTEST_END          0x07f00000
113
114 /* Early revs of this board will lock up hard when attempting
115  * to access the PMC registers, unless a JTAG debugger is
116  * connected, or some resistor modifications are made.
117  */
118 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
119
120 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
121 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
122
123 /*
124  * Device configurations
125  */
126
127 /* Vitesse 7385 */
128
129 #ifdef CONFIG_VSC7385_ENET
130
131 #define CONFIG_TSEC1
132
133 /* The flash address and size of the VSC7385 firmware image */
134 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
135 #define CONFIG_VSC7385_IMAGE_SIZE       8192
136
137 #endif
138
139 /*
140  * DDR Setup
141  */
142 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
143 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
144 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
145
146 /*
147  * Manually set up DDR parameters, as this board does not
148  * seem to have the SPD connected to I2C.
149  */
150 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
151 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
152                                 | CSCONFIG_ODT_RD_NEVER \
153                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
154                                 | CSCONFIG_ROW_BIT_13 \
155                                 | CSCONFIG_COL_BIT_10)
156                                 /* 0x80010102 */
157
158 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
159 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
160                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
161                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
162                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
163                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
164                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
165                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
166                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
167                                 /* 0x00220802 */
168 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
169                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
170                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
171                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
172                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
173                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
174                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
175                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
176                                 /* 0x3835a322 */
177 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
178                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
179                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
180                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
181                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
182                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
183                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
184                                 /* 0x129048c6 */ /* P9-45,may need tuning */
185 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
186                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
187                                 /* 0x05100500 */
188 #if defined(CONFIG_DDR_2T_TIMING)
189 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
190                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
191                                 | SDRAM_CFG_DBW_32 \
192                                 | SDRAM_CFG_2T_EN)
193                                 /* 0x43088000 */
194 #else
195 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
196                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
197                                 | SDRAM_CFG_DBW_32)
198                                 /* 0x43080000 */
199 #endif
200 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
201 /* set burst length to 8 for 32-bit data path */
202 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
203                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
204                                 /* 0x44480632 */
205 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
206
207 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
208                                 /*0x02000000*/
209 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
210                                 | DDRCDR_PZ_NOMZ \
211                                 | DDRCDR_NZ_NOMZ \
212                                 | DDRCDR_M_ODR)
213
214 /*
215  * FLASH on the Local Bus
216  */
217 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
218 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
219 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
220 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
221 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
222 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
223 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
224
225 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
226                                         | BR_PS_16      /* 16 bit port */ \
227                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
228                                         | BR_V)         /* valid */
229 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
230                                 | OR_GPCM_XACS \
231                                 | OR_GPCM_SCY_9 \
232                                 | OR_GPCM_EHTR \
233                                 | OR_GPCM_EAD)
234                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
235                                         /* window base at flash base */
236 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
237                                         /* 16 MB window size */
238 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
239
240 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
241 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
242
243 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
244 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
245
246 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
247         !defined(CONFIG_SPL_BUILD)
248 #define CONFIG_SYS_RAMBOOT
249 #endif
250
251 #define CONFIG_SYS_INIT_RAM_LOCK        1
252 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
253 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
254
255 #define CONFIG_SYS_GBL_DATA_OFFSET      \
256                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
257 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
258
259 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
260 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)    /* Reserve 384 kB for Mon */
261 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
262
263 /*
264  * Local Bus LCRR and LBCR regs
265  */
266 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
267 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
268 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
269                                 | (0xFF << LBCR_BMT_SHIFT) \
270                                 | 0xF)  /* 0x0004ff0f */
271
272                                 /* LB refresh timer prescal, 266MHz/32 */
273 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
274
275 /* drivers/mtd/nand/nand.c */
276 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
277 #define CONFIG_SYS_NAND_BASE            0xFFF00000
278 #else
279 #define CONFIG_SYS_NAND_BASE            0xE2800000
280 #endif
281
282 #define CONFIG_MTD_DEVICE
283 #define CONFIG_MTD_PARTITION
284 #define CONFIG_CMD_MTDPARTS
285 #define MTDIDS_DEFAULT                  "nand0=e2800000.flash"
286 #define MTDPARTS_DEFAULT                \
287         "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
288
289 #define CONFIG_SYS_MAX_NAND_DEVICE      1
290 #define CONFIG_MTD_NAND_VERIFY_WRITE
291 #define CONFIG_CMD_NAND 1
292 #define CONFIG_NAND_FSL_ELBC 1
293 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
294 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
295
296
297 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
298                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
299                                 | BR_PS_8               /* 8 bit port */ \
300                                 | BR_MS_FCM             /* MSEL = FCM */ \
301                                 | BR_V)                 /* valid */
302 #define CONFIG_SYS_NAND_OR_PRELIM       \
303                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
304                                 | OR_FCM_CSCT \
305                                 | OR_FCM_CST \
306                                 | OR_FCM_CHT \
307                                 | OR_FCM_SCY_1 \
308                                 | OR_FCM_TRLX \
309                                 | OR_FCM_EHTR)
310                                 /* 0xFFFF8396 */
311
312 #ifdef CONFIG_NAND
313 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
314 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
315 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
316 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
317 #else
318 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
319 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
320 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
321 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
322 #endif
323
324 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
325 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
326
327 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
328 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
329
330 /* local bus write LED / read status buffer (BCSR) mapping */
331 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
332 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
333                                         /* map at 0xFA000000 on LCS3 */
334 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_BCSR_ADDR \
335                                         | BR_PS_8       /* 8 bit port */ \
336                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
337                                         | BR_V)         /* valid */
338                                         /* 0xFA000801 */
339 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
340                                         | OR_GPCM_CSNT \
341                                         | OR_GPCM_ACS_DIV2 \
342                                         | OR_GPCM_XACS \
343                                         | OR_GPCM_SCY_15 \
344                                         | OR_GPCM_TRLX_SET \
345                                         | OR_GPCM_EHTR_SET \
346                                         | OR_GPCM_EAD)
347                                         /* 0xFFFF8FF7 */
348 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_BCSR_ADDR
349 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
350
351 /* Vitesse 7385 */
352
353 #ifdef CONFIG_VSC7385_ENET
354
355                                         /* VSC7385 Base address on LCS2 */
356 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
357 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
358
359 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
360                                         | BR_PS_8       /* 8 bit port */ \
361                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
362                                         | BR_V)         /* valid */
363 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
364                                         | OR_GPCM_CSNT \
365                                         | OR_GPCM_XACS \
366                                         | OR_GPCM_SCY_15 \
367                                         | OR_GPCM_SETA \
368                                         | OR_GPCM_TRLX_SET \
369                                         | OR_GPCM_EHTR_SET \
370                                         | OR_GPCM_EAD)
371                                         /* 0xFFFE09FF */
372
373                                         /* Access window base at VSC7385 base */
374 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
375 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
376
377 #endif
378
379 /* pass open firmware flat tree */
380 #define CONFIG_OF_LIBFDT        1
381 #define CONFIG_OF_BOARD_SETUP   1
382 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
383
384 #define CONFIG_MPC83XX_GPIO 1
385 #define CONFIG_CMD_GPIO 1
386
387 /*
388  * Serial Port
389  */
390 #define CONFIG_CONS_INDEX       1
391 #define CONFIG_SYS_NS16550
392 #define CONFIG_SYS_NS16550_SERIAL
393 #define CONFIG_SYS_NS16550_REG_SIZE     1
394
395 #define CONFIG_SYS_BAUDRATE_TABLE       \
396         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
397
398 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
399 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
400
401 /* Use the HUSH parser */
402 #define CONFIG_SYS_HUSH_PARSER
403
404 /* I2C */
405 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
406 #define CONFIG_FSL_I2C
407 #define CONFIG_I2C_MULTI_BUS
408 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
409 #define CONFIG_SYS_I2C_SLAVE    0x7F
410 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
411 #define CONFIG_SYS_I2C_OFFSET   0x3000
412 #define CONFIG_SYS_I2C2_OFFSET  0x3100
413
414 /*
415  * General PCI
416  * Addresses are mapped 1-1.
417  */
418 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
419 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
420 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
421 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
422 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
423 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
424 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
425 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
426 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
427
428 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
429 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
430
431 /*
432  * TSEC
433  */
434 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
435
436 #define CONFIG_GMII                     /* MII PHY management */
437
438 #ifdef CONFIG_TSEC1
439 #define CONFIG_HAS_ETH0
440 #define CONFIG_TSEC1_NAME       "TSEC0"
441 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
442 #define TSEC1_PHY_ADDR          0x1c
443 #define TSEC1_FLAGS             TSEC_GIGABIT
444 #define TSEC1_PHYIDX            0
445 #endif
446
447 #ifdef CONFIG_TSEC2
448 #define CONFIG_HAS_ETH1
449 #define CONFIG_TSEC2_NAME       "TSEC1"
450 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
451 #define TSEC2_PHY_ADDR          4
452 #define TSEC2_FLAGS             TSEC_GIGABIT
453 #define TSEC2_PHYIDX            0
454 #endif
455
456
457 /* Options are: TSEC[0-1] */
458 #define CONFIG_ETHPRIME                 "TSEC1"
459
460 /*
461  * Configure on-board RTC
462  */
463 #define CONFIG_RTC_DS1337
464 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
465
466 /*
467  * Environment
468  */
469 #if defined(CONFIG_NAND)
470         #define CONFIG_ENV_IS_IN_NAND   1
471         #define CONFIG_ENV_OFFSET               (512 * 1024)
472         #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
473         #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
474         #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
475         #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
476         #define CONFIG_ENV_OFFSET_REDUND        \
477                                         (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
478 #elif !defined(CONFIG_SYS_RAMBOOT)
479         #define CONFIG_ENV_IS_IN_FLASH  1
480         #define CONFIG_ENV_ADDR         \
481                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
482         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
483         #define CONFIG_ENV_SIZE         0x2000
484
485 /* Address and size of Redundant Environment Sector */
486 #else
487         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
488         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
489         #define CONFIG_ENV_SIZE         0x2000
490 #endif
491
492 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
493 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
494
495 /*
496  * BOOTP options
497  */
498 #define CONFIG_BOOTP_BOOTFILESIZE
499 #define CONFIG_BOOTP_BOOTPATH
500 #define CONFIG_BOOTP_GATEWAY
501 #define CONFIG_BOOTP_HOSTNAME
502
503
504 /*
505  * Command line configuration.
506  */
507 #include <config_cmd_default.h>
508
509 #define CONFIG_CMD_PING
510 #define CONFIG_CMD_DHCP
511 #define CONFIG_CMD_I2C
512 #define CONFIG_CMD_MII
513 #define CONFIG_CMD_DATE
514 #define CONFIG_CMD_PCI
515
516 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND)
517     #undef CONFIG_CMD_SAVEENV
518     #undef CONFIG_CMD_LOADS
519 #endif
520
521 #define CONFIG_CMDLINE_EDITING 1
522 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
523
524 /*
525  * Miscellaneous configurable options
526  */
527 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
528 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
529 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
530 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
531
532                                                 /* Print Buffer Size */
533 #define CONFIG_SYS_PBSIZE       \
534                         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
535 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
536                                 /* Boot Argument Buffer Size */
537 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
538 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
539
540 /*
541  * For booting Linux, the board info and command line data
542  * have to be in the first 256 MB of memory, since this is
543  * the maximum mapped by the Linux kernel during initialization.
544  */
545                                 /* Initial Memory map for Linux*/
546 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
547
548 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
549
550 #ifdef CONFIG_SYS_66MHZ
551
552 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
553 /* 0x62040000 */
554 #define CONFIG_SYS_HRCW_LOW (\
555         0x20000000 /* reserved, must be set */ |\
556         HRCWL_DDRCM |\
557         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
558         HRCWL_DDR_TO_SCB_CLK_2X1 |\
559         HRCWL_CSB_TO_CLKIN_2X1 |\
560         HRCWL_CORE_TO_CSB_2X1)
561
562 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
563
564 #elif defined(CONFIG_SYS_33MHZ)
565
566 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
567 /* 0x65040000 */
568 #define CONFIG_SYS_HRCW_LOW (\
569         0x20000000 /* reserved, must be set */ |\
570         HRCWL_DDRCM |\
571         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
572         HRCWL_DDR_TO_SCB_CLK_2X1 |\
573         HRCWL_CSB_TO_CLKIN_5X1 |\
574         HRCWL_CORE_TO_CSB_2X1)
575
576 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
577
578 #endif
579
580 #define CONFIG_SYS_HRCW_HIGH_BASE (\
581         HRCWH_PCI_HOST |\
582         HRCWH_PCI1_ARBITER_ENABLE |\
583         HRCWH_CORE_ENABLE |\
584         HRCWH_BOOTSEQ_DISABLE |\
585         HRCWH_SW_WATCHDOG_DISABLE |\
586         HRCWH_TSEC1M_IN_RGMII |\
587         HRCWH_TSEC2M_IN_RGMII |\
588         HRCWH_BIG_ENDIAN)
589
590 #ifdef CONFIG_NAND
591 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
592                        HRCWH_FROM_0XFFF00100 |\
593                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
594                        HRCWH_RL_EXT_NAND)
595 #else
596 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
597                        HRCWH_FROM_0X00000100 |\
598                        HRCWH_ROM_LOC_LOCAL_16BIT |\
599                        HRCWH_RL_EXT_LEGACY)
600 #endif
601
602 /* System IO Config */
603 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
604                         /* Enable Internal USB Phy and GPIO on LCD Connector */
605 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
606
607 #define CONFIG_SYS_HID0_INIT    0x000000000
608 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
609                                  HID0_ENABLE_INSTRUCTION_CACHE | \
610                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
611
612 #define CONFIG_SYS_HID2 HID2_HBE
613
614 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
615
616 /* DDR @ 0x00000000 */
617 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
618 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
619                                 | BATU_BL_256M \
620                                 | BATU_VS \
621                                 | BATU_VP)
622
623 /* PCI @ 0x80000000 */
624 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
625 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
626                                 | BATU_BL_256M \
627                                 | BATU_VS \
628                                 | BATU_VP)
629 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
630                                 | BATL_PP_RW \
631                                 | BATL_CACHEINHIBIT \
632                                 | BATL_GUARDEDSTORAGE)
633 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
634                                 | BATU_BL_256M \
635                                 | BATU_VS \
636                                 | BATU_VP)
637
638 /* PCI2 not supported on 8313 */
639 #define CONFIG_SYS_IBAT3L       (0)
640 #define CONFIG_SYS_IBAT3U       (0)
641 #define CONFIG_SYS_IBAT4L       (0)
642 #define CONFIG_SYS_IBAT4U       (0)
643
644 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
645 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
646                                 | BATL_PP_RW \
647                                 | BATL_CACHEINHIBIT \
648                                 | BATL_GUARDEDSTORAGE)
649 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
650                                 | BATU_BL_256M \
651                                 | BATU_VS \
652                                 | BATU_VP)
653
654 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
655 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
656 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
657
658 #define CONFIG_SYS_IBAT7L       (0)
659 #define CONFIG_SYS_IBAT7U       (0)
660
661 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
662 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
663 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
664 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
665 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
666 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
667 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
668 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
669 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
670 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
671 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
672 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
673 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
674 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
675 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
676 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
677
678 /*
679  * Environment Configuration
680  */
681 #define CONFIG_ENV_OVERWRITE
682
683 #define CONFIG_NETDEV           "eth1"
684
685 #define CONFIG_HOSTNAME         mpc8313erdb
686 #define CONFIG_ROOTPATH         "/nfs/root/path"
687 #define CONFIG_BOOTFILE         "uImage"
688                                 /* U-Boot image on TFTP server */
689 #define CONFIG_UBOOTPATH        "u-boot.bin"
690 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
691
692                                 /* default location for tftp and bootm */
693 #define CONFIG_LOADADDR         800000
694 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
695 #define CONFIG_BAUDRATE         115200
696
697 #define CONFIG_EXTRA_ENV_SETTINGS \
698         "netdev=" CONFIG_NETDEV "\0"                                    \
699         "ethprime=TSEC1\0"                                              \
700         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
701         "tftpflash=tftpboot $loadaddr $uboot; "                         \
702                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
703                         " +$filesize; " \
704                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
705                         " +$filesize; " \
706                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
707                         " $filesize; "  \
708                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
709                         " +$filesize; " \
710                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
711                         " $filesize\0"  \
712         "fdtaddr=780000\0"                                              \
713         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
714         "console=ttyS0\0"                                               \
715         "setbootargs=setenv bootargs "                                  \
716                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
717         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
718                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
719                                                         "$netdev:off " \
720                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
721
722 #define CONFIG_NFSBOOTCOMMAND                                           \
723         "setenv rootdev /dev/nfs;"                                      \
724         "run setbootargs;"                                              \
725         "run setipargs;"                                                \
726         "tftp $loadaddr $bootfile;"                                     \
727         "tftp $fdtaddr $fdtfile;"                                       \
728         "bootm $loadaddr - $fdtaddr"
729
730 #define CONFIG_RAMBOOTCOMMAND                                           \
731         "setenv rootdev /dev/ram;"                                      \
732         "run setbootargs;"                                              \
733         "tftp $ramdiskaddr $ramdiskfile;"                               \
734         "tftp $loadaddr $bootfile;"                                     \
735         "tftp $fdtaddr $fdtfile;"                                       \
736         "bootm $loadaddr $ramdiskaddr $fdtaddr"
737
738 #endif  /* __CONFIG_H */