Merge branch 'master' of git://git.denx.de/u-boot-usb
[platform/kernel/u-boot.git] / include / configs / MPC8313ERDB.h
1 /*
2  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 /*
7  * mpc8313epb board configuration file
8  */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 /*
14  * High Level Configuration Options
15  */
16 #define CONFIG_E300             1
17 #define CONFIG_MPC831x          1
18 #define CONFIG_MPC8313          1
19 #define CONFIG_MPC8313ERDB      1
20
21 #ifdef CONFIG_NAND
22 #define CONFIG_SPL_INIT_MINIMAL
23 #define CONFIG_SPL_SERIAL_SUPPORT
24 #define CONFIG_SPL_NAND_SUPPORT
25 #define CONFIG_SPL_FLUSH_IMAGE
26 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
27 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
28
29 #ifdef CONFIG_SPL_BUILD
30 #define CONFIG_NS16550_MIN_FUNCTIONS
31 #endif
32
33 #define CONFIG_SYS_TEXT_BASE    0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
34 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
35 #define CONFIG_SPL_MAX_SIZE     (4 * 1024)
36 #define CONFIG_SPL_PAD_TO       0x4000
37
38 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
39 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
40 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
41 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
42 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
43 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
44
45 #ifdef CONFIG_SPL_BUILD
46 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
47 #endif
48
49 #endif /* CONFIG_NAND */
50
51 #ifndef CONFIG_SYS_TEXT_BASE
52 #define CONFIG_SYS_TEXT_BASE    0xFE000000
53 #endif
54
55 #ifndef CONFIG_SYS_MONITOR_BASE
56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
57 #endif
58
59 #define CONFIG_PCI
60 #define CONFIG_PCI_INDIRECT_BRIDGE
61 #define CONFIG_FSL_ELBC 1
62
63 #define CONFIG_MISC_INIT_R
64
65 /*
66  * On-board devices
67  *
68  * TSEC1 is VSC switch
69  * TSEC2 is SoC TSEC
70  */
71 #define CONFIG_VSC7385_ENET
72 #define CONFIG_TSEC2
73
74 #ifdef CONFIG_SYS_66MHZ
75 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
76 #elif defined(CONFIG_SYS_33MHZ)
77 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
78 #else
79 #error Unknown oscillator frequency.
80 #endif
81
82 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
83
84 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f */
85 #define CONFIG_BOARD_EARLY_INIT_R               /* call board_early_init_r */
86
87 #define CONFIG_SYS_IMMR         0xE0000000
88
89 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
90 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
91 #endif
92
93 #define CONFIG_SYS_MEMTEST_START        0x00001000
94 #define CONFIG_SYS_MEMTEST_END          0x07f00000
95
96 /* Early revs of this board will lock up hard when attempting
97  * to access the PMC registers, unless a JTAG debugger is
98  * connected, or some resistor modifications are made.
99  */
100 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
101
102 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
103 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
104
105 /*
106  * Device configurations
107  */
108
109 /* Vitesse 7385 */
110
111 #ifdef CONFIG_VSC7385_ENET
112
113 #define CONFIG_TSEC1
114
115 /* The flash address and size of the VSC7385 firmware image */
116 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
117 #define CONFIG_VSC7385_IMAGE_SIZE       8192
118
119 #endif
120
121 /*
122  * DDR Setup
123  */
124 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
125 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
126 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
127
128 /*
129  * Manually set up DDR parameters, as this board does not
130  * seem to have the SPD connected to I2C.
131  */
132 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
133 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
134                                 | CSCONFIG_ODT_RD_NEVER \
135                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
136                                 | CSCONFIG_ROW_BIT_13 \
137                                 | CSCONFIG_COL_BIT_10)
138                                 /* 0x80010102 */
139
140 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
141 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
142                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
143                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
144                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
145                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
146                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
147                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
148                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
149                                 /* 0x00220802 */
150 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
151                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
152                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
153                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
154                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
155                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
156                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
157                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
158                                 /* 0x3835a322 */
159 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
160                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
161                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
162                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
163                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
164                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
165                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
166                                 /* 0x129048c6 */ /* P9-45,may need tuning */
167 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
168                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
169                                 /* 0x05100500 */
170 #if defined(CONFIG_DDR_2T_TIMING)
171 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
172                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
173                                 | SDRAM_CFG_DBW_32 \
174                                 | SDRAM_CFG_2T_EN)
175                                 /* 0x43088000 */
176 #else
177 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
178                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
179                                 | SDRAM_CFG_DBW_32)
180                                 /* 0x43080000 */
181 #endif
182 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
183 /* set burst length to 8 for 32-bit data path */
184 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
185                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
186                                 /* 0x44480632 */
187 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
188
189 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
190                                 /*0x02000000*/
191 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
192                                 | DDRCDR_PZ_NOMZ \
193                                 | DDRCDR_NZ_NOMZ \
194                                 | DDRCDR_M_ODR)
195
196 /*
197  * FLASH on the Local Bus
198  */
199 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
200 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
201 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
202 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
203 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
204 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
205 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
206
207 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
208                                         | BR_PS_16      /* 16 bit port */ \
209                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
210                                         | BR_V)         /* valid */
211 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
212                                 | OR_GPCM_XACS \
213                                 | OR_GPCM_SCY_9 \
214                                 | OR_GPCM_EHTR \
215                                 | OR_GPCM_EAD)
216                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
217                                         /* window base at flash base */
218 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
219                                         /* 16 MB window size */
220 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
221
222 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
223 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
224
225 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
226 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
227
228 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
229         !defined(CONFIG_SPL_BUILD)
230 #define CONFIG_SYS_RAMBOOT
231 #endif
232
233 #define CONFIG_SYS_INIT_RAM_LOCK        1
234 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
235 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
236
237 #define CONFIG_SYS_GBL_DATA_OFFSET      \
238                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
239 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
240
241 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
242 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)    /* Reserve 384 kB for Mon */
243 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
244
245 /*
246  * Local Bus LCRR and LBCR regs
247  */
248 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
249 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
250 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
251                                 | (0xFF << LBCR_BMT_SHIFT) \
252                                 | 0xF)  /* 0x0004ff0f */
253
254                                 /* LB refresh timer prescal, 266MHz/32 */
255 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
256
257 /* drivers/mtd/nand/nand.c */
258 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
259 #define CONFIG_SYS_NAND_BASE            0xFFF00000
260 #else
261 #define CONFIG_SYS_NAND_BASE            0xE2800000
262 #endif
263
264 #define CONFIG_MTD_DEVICE
265 #define CONFIG_MTD_PARTITION
266 #define CONFIG_CMD_MTDPARTS
267 #define MTDIDS_DEFAULT                  "nand0=e2800000.flash"
268 #define MTDPARTS_DEFAULT                \
269         "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
270
271 #define CONFIG_SYS_MAX_NAND_DEVICE      1
272 #define CONFIG_MTD_NAND_VERIFY_WRITE
273 #define CONFIG_CMD_NAND 1
274 #define CONFIG_NAND_FSL_ELBC 1
275 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
276 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
277
278
279 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
280                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
281                                 | BR_PS_8               /* 8 bit port */ \
282                                 | BR_MS_FCM             /* MSEL = FCM */ \
283                                 | BR_V)                 /* valid */
284 #define CONFIG_SYS_NAND_OR_PRELIM       \
285                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
286                                 | OR_FCM_CSCT \
287                                 | OR_FCM_CST \
288                                 | OR_FCM_CHT \
289                                 | OR_FCM_SCY_1 \
290                                 | OR_FCM_TRLX \
291                                 | OR_FCM_EHTR)
292                                 /* 0xFFFF8396 */
293
294 #ifdef CONFIG_NAND
295 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
296 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
297 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
298 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
299 #else
300 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
301 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
302 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
303 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
304 #endif
305
306 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
307 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
308
309 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
310 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
311
312 /* local bus write LED / read status buffer (BCSR) mapping */
313 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
314 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
315                                         /* map at 0xFA000000 on LCS3 */
316 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_BCSR_ADDR \
317                                         | BR_PS_8       /* 8 bit port */ \
318                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
319                                         | BR_V)         /* valid */
320                                         /* 0xFA000801 */
321 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
322                                         | OR_GPCM_CSNT \
323                                         | OR_GPCM_ACS_DIV2 \
324                                         | OR_GPCM_XACS \
325                                         | OR_GPCM_SCY_15 \
326                                         | OR_GPCM_TRLX_SET \
327                                         | OR_GPCM_EHTR_SET \
328                                         | OR_GPCM_EAD)
329                                         /* 0xFFFF8FF7 */
330 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_BCSR_ADDR
331 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
332
333 /* Vitesse 7385 */
334
335 #ifdef CONFIG_VSC7385_ENET
336
337                                         /* VSC7385 Base address on LCS2 */
338 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
339 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
340
341 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
342                                         | BR_PS_8       /* 8 bit port */ \
343                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
344                                         | BR_V)         /* valid */
345 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
346                                         | OR_GPCM_CSNT \
347                                         | OR_GPCM_XACS \
348                                         | OR_GPCM_SCY_15 \
349                                         | OR_GPCM_SETA \
350                                         | OR_GPCM_TRLX_SET \
351                                         | OR_GPCM_EHTR_SET \
352                                         | OR_GPCM_EAD)
353                                         /* 0xFFFE09FF */
354
355                                         /* Access window base at VSC7385 base */
356 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
357 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
358
359 #endif
360
361 /* pass open firmware flat tree */
362 #define CONFIG_OF_LIBFDT        1
363 #define CONFIG_OF_BOARD_SETUP   1
364 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
365
366 #define CONFIG_MPC83XX_GPIO 1
367 #define CONFIG_CMD_GPIO 1
368
369 /*
370  * Serial Port
371  */
372 #define CONFIG_CONS_INDEX       1
373 #define CONFIG_SYS_NS16550
374 #define CONFIG_SYS_NS16550_SERIAL
375 #define CONFIG_SYS_NS16550_REG_SIZE     1
376
377 #define CONFIG_SYS_BAUDRATE_TABLE       \
378         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
379
380 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
381 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
382
383 /* Use the HUSH parser */
384 #define CONFIG_SYS_HUSH_PARSER
385
386 /* I2C */
387 #define CONFIG_SYS_I2C
388 #define CONFIG_SYS_I2C_FSL
389 #define CONFIG_SYS_FSL_I2C_SPEED        400000
390 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
391 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
392 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
393 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
394 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
395 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
396
397 /*
398  * General PCI
399  * Addresses are mapped 1-1.
400  */
401 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
402 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
403 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
404 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
405 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
406 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
407 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
408 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
409 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
410
411 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
412 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
413
414 /*
415  * TSEC
416  */
417 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
418
419 #define CONFIG_GMII                     /* MII PHY management */
420
421 #ifdef CONFIG_TSEC1
422 #define CONFIG_HAS_ETH0
423 #define CONFIG_TSEC1_NAME       "TSEC0"
424 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
425 #define TSEC1_PHY_ADDR          0x1c
426 #define TSEC1_FLAGS             TSEC_GIGABIT
427 #define TSEC1_PHYIDX            0
428 #endif
429
430 #ifdef CONFIG_TSEC2
431 #define CONFIG_HAS_ETH1
432 #define CONFIG_TSEC2_NAME       "TSEC1"
433 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
434 #define TSEC2_PHY_ADDR          4
435 #define TSEC2_FLAGS             TSEC_GIGABIT
436 #define TSEC2_PHYIDX            0
437 #endif
438
439
440 /* Options are: TSEC[0-1] */
441 #define CONFIG_ETHPRIME                 "TSEC1"
442
443 /*
444  * Configure on-board RTC
445  */
446 #define CONFIG_RTC_DS1337
447 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
448
449 /*
450  * Environment
451  */
452 #if defined(CONFIG_NAND)
453         #define CONFIG_ENV_IS_IN_NAND   1
454         #define CONFIG_ENV_OFFSET               (512 * 1024)
455         #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
456         #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
457         #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
458         #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
459         #define CONFIG_ENV_OFFSET_REDUND        \
460                                         (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
461 #elif !defined(CONFIG_SYS_RAMBOOT)
462         #define CONFIG_ENV_IS_IN_FLASH  1
463         #define CONFIG_ENV_ADDR         \
464                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
465         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
466         #define CONFIG_ENV_SIZE         0x2000
467
468 /* Address and size of Redundant Environment Sector */
469 #else
470         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
471         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
472         #define CONFIG_ENV_SIZE         0x2000
473 #endif
474
475 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
476 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
477
478 /*
479  * BOOTP options
480  */
481 #define CONFIG_BOOTP_BOOTFILESIZE
482 #define CONFIG_BOOTP_BOOTPATH
483 #define CONFIG_BOOTP_GATEWAY
484 #define CONFIG_BOOTP_HOSTNAME
485
486
487 /*
488  * Command line configuration.
489  */
490 #include <config_cmd_default.h>
491
492 #define CONFIG_CMD_PING
493 #define CONFIG_CMD_DHCP
494 #define CONFIG_CMD_I2C
495 #define CONFIG_CMD_MII
496 #define CONFIG_CMD_DATE
497 #define CONFIG_CMD_PCI
498
499 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND)
500     #undef CONFIG_CMD_SAVEENV
501     #undef CONFIG_CMD_LOADS
502 #endif
503
504 #define CONFIG_CMDLINE_EDITING 1
505 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
506
507 /*
508  * Miscellaneous configurable options
509  */
510 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
511 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
512 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
513
514                                                 /* Print Buffer Size */
515 #define CONFIG_SYS_PBSIZE       \
516                         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
517 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
518                                 /* Boot Argument Buffer Size */
519 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
520
521 /*
522  * For booting Linux, the board info and command line data
523  * have to be in the first 256 MB of memory, since this is
524  * the maximum mapped by the Linux kernel during initialization.
525  */
526                                 /* Initial Memory map for Linux*/
527 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
528
529 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
530
531 #ifdef CONFIG_SYS_66MHZ
532
533 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
534 /* 0x62040000 */
535 #define CONFIG_SYS_HRCW_LOW (\
536         0x20000000 /* reserved, must be set */ |\
537         HRCWL_DDRCM |\
538         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
539         HRCWL_DDR_TO_SCB_CLK_2X1 |\
540         HRCWL_CSB_TO_CLKIN_2X1 |\
541         HRCWL_CORE_TO_CSB_2X1)
542
543 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
544
545 #elif defined(CONFIG_SYS_33MHZ)
546
547 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
548 /* 0x65040000 */
549 #define CONFIG_SYS_HRCW_LOW (\
550         0x20000000 /* reserved, must be set */ |\
551         HRCWL_DDRCM |\
552         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
553         HRCWL_DDR_TO_SCB_CLK_2X1 |\
554         HRCWL_CSB_TO_CLKIN_5X1 |\
555         HRCWL_CORE_TO_CSB_2X1)
556
557 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
558
559 #endif
560
561 #define CONFIG_SYS_HRCW_HIGH_BASE (\
562         HRCWH_PCI_HOST |\
563         HRCWH_PCI1_ARBITER_ENABLE |\
564         HRCWH_CORE_ENABLE |\
565         HRCWH_BOOTSEQ_DISABLE |\
566         HRCWH_SW_WATCHDOG_DISABLE |\
567         HRCWH_TSEC1M_IN_RGMII |\
568         HRCWH_TSEC2M_IN_RGMII |\
569         HRCWH_BIG_ENDIAN)
570
571 #ifdef CONFIG_NAND
572 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
573                        HRCWH_FROM_0XFFF00100 |\
574                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
575                        HRCWH_RL_EXT_NAND)
576 #else
577 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
578                        HRCWH_FROM_0X00000100 |\
579                        HRCWH_ROM_LOC_LOCAL_16BIT |\
580                        HRCWH_RL_EXT_LEGACY)
581 #endif
582
583 /* System IO Config */
584 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
585                         /* Enable Internal USB Phy and GPIO on LCD Connector */
586 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
587
588 #define CONFIG_SYS_HID0_INIT    0x000000000
589 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
590                                  HID0_ENABLE_INSTRUCTION_CACHE | \
591                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
592
593 #define CONFIG_SYS_HID2 HID2_HBE
594
595 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
596
597 /* DDR @ 0x00000000 */
598 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
599 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
600                                 | BATU_BL_256M \
601                                 | BATU_VS \
602                                 | BATU_VP)
603
604 /* PCI @ 0x80000000 */
605 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
606 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
607                                 | BATU_BL_256M \
608                                 | BATU_VS \
609                                 | BATU_VP)
610 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
611                                 | BATL_PP_RW \
612                                 | BATL_CACHEINHIBIT \
613                                 | BATL_GUARDEDSTORAGE)
614 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
615                                 | BATU_BL_256M \
616                                 | BATU_VS \
617                                 | BATU_VP)
618
619 /* PCI2 not supported on 8313 */
620 #define CONFIG_SYS_IBAT3L       (0)
621 #define CONFIG_SYS_IBAT3U       (0)
622 #define CONFIG_SYS_IBAT4L       (0)
623 #define CONFIG_SYS_IBAT4U       (0)
624
625 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
626 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
627                                 | BATL_PP_RW \
628                                 | BATL_CACHEINHIBIT \
629                                 | BATL_GUARDEDSTORAGE)
630 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
631                                 | BATU_BL_256M \
632                                 | BATU_VS \
633                                 | BATU_VP)
634
635 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
636 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
637 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
638
639 #define CONFIG_SYS_IBAT7L       (0)
640 #define CONFIG_SYS_IBAT7U       (0)
641
642 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
643 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
644 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
645 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
646 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
647 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
648 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
649 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
650 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
651 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
652 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
653 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
654 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
655 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
656 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
657 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
658
659 /*
660  * Environment Configuration
661  */
662 #define CONFIG_ENV_OVERWRITE
663
664 #define CONFIG_NETDEV           "eth1"
665
666 #define CONFIG_HOSTNAME         mpc8313erdb
667 #define CONFIG_ROOTPATH         "/nfs/root/path"
668 #define CONFIG_BOOTFILE         "uImage"
669                                 /* U-Boot image on TFTP server */
670 #define CONFIG_UBOOTPATH        "u-boot.bin"
671 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
672
673                                 /* default location for tftp and bootm */
674 #define CONFIG_LOADADDR         800000
675 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
676 #define CONFIG_BAUDRATE         115200
677
678 #define CONFIG_EXTRA_ENV_SETTINGS \
679         "netdev=" CONFIG_NETDEV "\0"                                    \
680         "ethprime=TSEC1\0"                                              \
681         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
682         "tftpflash=tftpboot $loadaddr $uboot; "                         \
683                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
684                         " +$filesize; " \
685                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
686                         " +$filesize; " \
687                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
688                         " $filesize; "  \
689                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
690                         " +$filesize; " \
691                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
692                         " $filesize\0"  \
693         "fdtaddr=780000\0"                                              \
694         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
695         "console=ttyS0\0"                                               \
696         "setbootargs=setenv bootargs "                                  \
697                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
698         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
699                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
700                                                         "$netdev:off " \
701                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
702
703 #define CONFIG_NFSBOOTCOMMAND                                           \
704         "setenv rootdev /dev/nfs;"                                      \
705         "run setbootargs;"                                              \
706         "run setipargs;"                                                \
707         "tftp $loadaddr $bootfile;"                                     \
708         "tftp $fdtaddr $fdtfile;"                                       \
709         "bootm $loadaddr - $fdtaddr"
710
711 #define CONFIG_RAMBOOTCOMMAND                                           \
712         "setenv rootdev /dev/ram;"                                      \
713         "run setbootargs;"                                              \
714         "tftp $ramdiskaddr $ramdiskfile;"                               \
715         "tftp $loadaddr $bootfile;"                                     \
716         "tftp $fdtaddr $fdtfile;"                                       \
717         "bootm $loadaddr $ramdiskaddr $fdtaddr"
718
719 #endif  /* __CONFIG_H */