include/configs/MPC8313ERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   4  */
   5 /*
   6  * mpc8313epb board configuration file
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1
  16 #define CONFIG_MPC8313ERDB      1
  17
  18 #ifdef CONFIG_NAND
  19 #define CONFIG_SPL_INIT_MINIMAL
  20 #define CONFIG_SPL_FLUSH_IMAGE
  21 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  22 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
  23
  24 #ifdef CONFIG_SPL_BUILD
  25 #define CONFIG_NS16550_MIN_FUNCTIONS
  26 #endif
  27
  28 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  29 #define CONFIG_SPL_MAX_SIZE     (4 * 1024)
  30 #define CONFIG_SPL_PAD_TO       0x4000
  31
  32 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  33 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  34 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  35 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  36 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  37 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  38
  39 #ifdef CONFIG_SPL_BUILD
  40 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  41 #endif
  42
  43 #endif /* CONFIG_NAND */
  44
  45 #ifndef CONFIG_SYS_MONITOR_BASE
  46 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  47 #endif
  48
  49 #define CONFIG_PCI_INDIRECT_BRIDGE
  50 #define CONFIG_FSL_ELBC 1
  51
  52 /*
  53  * On-board devices
  54  *
  55  * TSEC1 is VSC switch
  56  * TSEC2 is SoC TSEC
  57  */
  58 #define CONFIG_VSC7385_ENET
  59 #define CONFIG_TSEC2
  60
  61 #ifdef CONFIG_SYS_66MHZ
  62 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  63 #elif defined(CONFIG_SYS_33MHZ)
  64 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
  65 #else
  66 #error Unknown oscillator frequency.
  67 #endif
  68
  69 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  70
  71 #define CONFIG_SYS_IMMR         0xE0000000
  72
  73 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
  74 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
  75 #endif
  76
  77 #define CONFIG_SYS_MEMTEST_START        0x00001000
  78 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  79
  80 /* Early revs of this board will lock up hard when attempting
  81  * to access the PMC registers, unless a JTAG debugger is
  82  * connected, or some resistor modifications are made.
  83  */
  84 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  85
  86 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  87 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  88
  89 /*
  90  * Device configurations
  91  */
  92
  93 /* Vitesse 7385 */
  94
  95 #ifdef CONFIG_VSC7385_ENET
  96
  97 #define CONFIG_TSEC1
  98
  99 /* The flash address and size of the VSC7385 firmware image */
 100 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 101 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 102
 103 #endif
 104
 105 /*
 106  * DDR Setup
 107  */
 108 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 109 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 110 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 111
 112 /*
 113  * Manually set up DDR parameters, as this board does not
 114  * seem to have the SPD connected to I2C.
 115  */
 116 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
 117 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 118                                 | CSCONFIG_ODT_RD_NEVER \
 119                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 120                                 | CSCONFIG_ROW_BIT_13 \
 121                                 | CSCONFIG_COL_BIT_10)
 122                                 /* 0x80010102 */
 123
 124 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 125 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 126                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 127                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 128                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 129                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 130                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 131                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 132                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 133                                 /* 0x00220802 */
 134 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 135                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 136                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 137                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 138                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
 139                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 140                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 141                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 142                                 /* 0x3835a322 */
 143 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 144                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 145                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 146                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 147                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 148                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 149                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 150                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 151 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 152                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 153                                 /* 0x05100500 */
 154 #if defined(CONFIG_DDR_2T_TIMING)
 155 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 156                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 157                                 | SDRAM_CFG_DBW_32 \
 158                                 | SDRAM_CFG_2T_EN)
 159                                 /* 0x43088000 */
 160 #else
 161 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 162                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 163                                 | SDRAM_CFG_DBW_32)
 164                                 /* 0x43080000 */
 165 #endif
 166 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 167 /* set burst length to 8 for 32-bit data path */
 168 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 169                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 170                                 /* 0x44480632 */
 171 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 172
 173 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 174                                 /*0x02000000*/
 175 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 176                                 | DDRCDR_PZ_NOMZ \
 177                                 | DDRCDR_NZ_NOMZ \
 178                                 | DDRCDR_M_ODR)
 179
 180 /*
 181  * FLASH on the Local Bus
 182  */
 183 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 184 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 185 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 186
 187 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
 188                                         | BR_PS_16      /* 16 bit port */ \
 189                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 190                                         | BR_V)         /* valid */
 191 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 192                                 | OR_GPCM_XACS \
 193                                 | OR_GPCM_SCY_9 \
 194                                 | OR_GPCM_EHTR \
 195                                 | OR_GPCM_EAD)
 196                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
 197                                         /* window base at flash base */
 198 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 199                                         /* 16 MB window size */
 200 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 201
 202 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 203 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 204
 205 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 206 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 207
 208 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 209         !defined(CONFIG_SPL_BUILD)
 210 #define CONFIG_SYS_RAMBOOT
 211 #endif
 212
 213 #define CONFIG_SYS_INIT_RAM_LOCK        1
 214 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 215 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 216
 217 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 218                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 219 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 220
 221 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 222 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 223 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 224
 225 /*
 226  * Local Bus LCRR and LBCR regs
 227  */
 228 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 229 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 230 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 231                                 | (0xFF << LBCR_BMT_SHIFT) \
 232                                 | 0xF)  /* 0x0004ff0f */
 233
 234                                 /* LB refresh timer prescal, 266MHz/32 */
 235 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
 236
 237 /* drivers/mtd/nand/raw/nand.c */
 238 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
 239 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 240 #else
 241 #define CONFIG_SYS_NAND_BASE            0xE2800000
 242 #endif
 243
 244 #define CONFIG_MTD_PARTITION
 245
 246 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 247 #define CONFIG_NAND_FSL_ELBC 1
 248 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 249 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 250
 251 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 252                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 253                                 | BR_PS_8               /* 8 bit port */ \
 254                                 | BR_MS_FCM             /* MSEL = FCM */ \
 255                                 | BR_V)                 /* valid */
 256 #define CONFIG_SYS_NAND_OR_PRELIM       \
 257                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 258                                 | OR_FCM_CSCT \
 259                                 | OR_FCM_CST \
 260                                 | OR_FCM_CHT \
 261                                 | OR_FCM_SCY_1 \
 262                                 | OR_FCM_TRLX \
 263                                 | OR_FCM_EHTR)
 264                                 /* 0xFFFF8396 */
 265
 266 #ifdef CONFIG_NAND
 267 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 268 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 269 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 270 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 271 #else
 272 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 273 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 274 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 275 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 276 #endif
 277
 278 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 279 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 280
 281 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 282 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 283
 284 /* local bus write LED / read status buffer (BCSR) mapping */
 285 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 286 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 287                                         /* map at 0xFA000000 on LCS3 */
 288 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_BCSR_ADDR \
 289                                         | BR_PS_8       /* 8 bit port */ \
 290                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 291                                         | BR_V)         /* valid */
 292                                         /* 0xFA000801 */
 293 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
 294                                         | OR_GPCM_CSNT \
 295                                         | OR_GPCM_ACS_DIV2 \
 296                                         | OR_GPCM_XACS \
 297                                         | OR_GPCM_SCY_15 \
 298                                         | OR_GPCM_TRLX_SET \
 299                                         | OR_GPCM_EHTR_SET \
 300                                         | OR_GPCM_EAD)
 301                                         /* 0xFFFF8FF7 */
 302 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_BCSR_ADDR
 303 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 304
 305 /* Vitesse 7385 */
 306
 307 #ifdef CONFIG_VSC7385_ENET
 308
 309                                         /* VSC7385 Base address on LCS2 */
 310 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 311 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 312
 313 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 314                                         | BR_PS_8       /* 8 bit port */ \
 315                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 316                                         | BR_V)         /* valid */
 317 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
 318                                         | OR_GPCM_CSNT \
 319                                         | OR_GPCM_XACS \
 320                                         | OR_GPCM_SCY_15 \
 321                                         | OR_GPCM_SETA \
 322                                         | OR_GPCM_TRLX_SET \
 323                                         | OR_GPCM_EHTR_SET \
 324                                         | OR_GPCM_EAD)
 325                                         /* 0xFFFE09FF */
 326
 327                                         /* Access window base at VSC7385 base */
 328 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 329 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 330
 331 #endif
 332
 333 #define CONFIG_MPC83XX_GPIO 1
 334
 335 /*
 336  * Serial Port
 337  */
 338 #define CONFIG_SYS_NS16550_SERIAL
 339 #define CONFIG_SYS_NS16550_REG_SIZE     1
 340
 341 #define CONFIG_SYS_BAUDRATE_TABLE       \
 342         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 343
 344 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 345 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 346
 347 /* I2C */
 348 #define CONFIG_SYS_I2C
 349 #define CONFIG_SYS_I2C_FSL
 350 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 351 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 352 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 353 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 354 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 355 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 356 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 357
 358 /*
 359  * General PCI
 360  * Addresses are mapped 1-1.
 361  */
 362 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 363 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 364 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 365 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 366 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 367 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 368 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 369 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 370 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 371
 372 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 373
 374 /*
 375  * TSEC
 376  */
 377
 378 #define CONFIG_GMII                     /* MII PHY management */
 379
 380 #ifdef CONFIG_TSEC1
 381 #define CONFIG_HAS_ETH0
 382 #define CONFIG_TSEC1_NAME       "TSEC0"
 383 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 384 #define TSEC1_PHY_ADDR          0x1c
 385 #define TSEC1_FLAGS             TSEC_GIGABIT
 386 #define TSEC1_PHYIDX            0
 387 #endif
 388
 389 #ifdef CONFIG_TSEC2
 390 #define CONFIG_HAS_ETH1
 391 #define CONFIG_TSEC2_NAME       "TSEC1"
 392 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 393 #define TSEC2_PHY_ADDR          4
 394 #define TSEC2_FLAGS             TSEC_GIGABIT
 395 #define TSEC2_PHYIDX            0
 396 #endif
 397
 398 /* Options are: TSEC[0-1] */
 399 #define CONFIG_ETHPRIME                 "TSEC1"
 400
 401 /*
 402  * Configure on-board RTC
 403  */
 404 #define CONFIG_RTC_DS1337
 405 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 406
 407 /*
 408  * Environment
 409  */
 410 #if defined(CONFIG_NAND)
 411         #define CONFIG_ENV_OFFSET               (512 * 1024)
 412         #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
 413         #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 414         #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 415         #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
 416         #define CONFIG_ENV_OFFSET_REDUND        \
 417                                         (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 418 #elif !defined(CONFIG_SYS_RAMBOOT)
 419         #define CONFIG_ENV_ADDR         \
 420                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 421         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 422         #define CONFIG_ENV_SIZE         0x2000
 423
 424 /* Address and size of Redundant Environment Sector */
 425 #else
 426         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 427         #define CONFIG_ENV_SIZE         0x2000
 428 #endif
 429
 430 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 431 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 432
 433 /*
 434  * BOOTP options
 435  */
 436 #define CONFIG_BOOTP_BOOTFILESIZE
 437
 438 /*
 439  * Command line configuration.
 440  */
 441
 442 /*
 443  * Miscellaneous configurable options
 444  */
 445 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 446 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 447
 448                                 /* Boot Argument Buffer Size */
 449 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 450
 451 /*
 452  * For booting Linux, the board info and command line data
 453  * have to be in the first 256 MB of memory, since this is
 454  * the maximum mapped by the Linux kernel during initialization.
 455  */
 456                                 /* Initial Memory map for Linux*/
 457 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 458 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 459
 460 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 461
 462 #ifdef CONFIG_SYS_66MHZ
 463
 464 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
 465 /* 0x62040000 */
 466 #define CONFIG_SYS_HRCW_LOW (\
 467         0x20000000 /* reserved, must be set */ |\
 468         HRCWL_DDRCM |\
 469         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 470         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 471         HRCWL_CSB_TO_CLKIN_2X1 |\
 472         HRCWL_CORE_TO_CSB_2X1)
 473
 474 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
 475
 476 #elif defined(CONFIG_SYS_33MHZ)
 477
 478 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
 479 /* 0x65040000 */
 480 #define CONFIG_SYS_HRCW_LOW (\
 481         0x20000000 /* reserved, must be set */ |\
 482         HRCWL_DDRCM |\
 483         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 484         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 485         HRCWL_CSB_TO_CLKIN_5X1 |\
 486         HRCWL_CORE_TO_CSB_2X1)
 487
 488 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
 489
 490 #endif
 491
 492 #define CONFIG_SYS_HRCW_HIGH_BASE (\
 493         HRCWH_PCI_HOST |\
 494         HRCWH_PCI1_ARBITER_ENABLE |\
 495         HRCWH_CORE_ENABLE |\
 496         HRCWH_BOOTSEQ_DISABLE |\
 497         HRCWH_SW_WATCHDOG_DISABLE |\
 498         HRCWH_TSEC1M_IN_RGMII |\
 499         HRCWH_TSEC2M_IN_RGMII |\
 500         HRCWH_BIG_ENDIAN)
 501
 502 #ifdef CONFIG_NAND
 503 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 504                        HRCWH_FROM_0XFFF00100 |\
 505                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
 506                        HRCWH_RL_EXT_NAND)
 507 #else
 508 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 509                        HRCWH_FROM_0X00000100 |\
 510                        HRCWH_ROM_LOC_LOCAL_16BIT |\
 511                        HRCWH_RL_EXT_LEGACY)
 512 #endif
 513
 514 /* System IO Config */
 515 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 516                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 517 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 518
 519 #define CONFIG_SYS_HID0_INIT    0x000000000
 520 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 521                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 522                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 523
 524 #define CONFIG_SYS_HID2 HID2_HBE
 525
 526 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 527
 528 /* DDR @ 0x00000000 */
 529 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 530 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 531                                 | BATU_BL_256M \
 532                                 | BATU_VS \
 533                                 | BATU_VP)
 534
 535 /* PCI @ 0x80000000 */
 536 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 537 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 538                                 | BATU_BL_256M \
 539                                 | BATU_VS \
 540                                 | BATU_VP)
 541 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 542                                 | BATL_PP_RW \
 543                                 | BATL_CACHEINHIBIT \
 544                                 | BATL_GUARDEDSTORAGE)
 545 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 546                                 | BATU_BL_256M \
 547                                 | BATU_VS \
 548                                 | BATU_VP)
 549
 550 /* PCI2 not supported on 8313 */
 551 #define CONFIG_SYS_IBAT3L       (0)
 552 #define CONFIG_SYS_IBAT3U       (0)
 553 #define CONFIG_SYS_IBAT4L       (0)
 554 #define CONFIG_SYS_IBAT4U       (0)
 555
 556 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 557 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 558                                 | BATL_PP_RW \
 559                                 | BATL_CACHEINHIBIT \
 560                                 | BATL_GUARDEDSTORAGE)
 561 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 562                                 | BATU_BL_256M \
 563                                 | BATU_VS \
 564                                 | BATU_VP)
 565
 566 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 567 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 568 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 569
 570 #define CONFIG_SYS_IBAT7L       (0)
 571 #define CONFIG_SYS_IBAT7U       (0)
 572
 573 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 574 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 575 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 576 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 577 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 578 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 579 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 580 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 581 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 582 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 583 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 584 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 585 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 586 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 587 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 588 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 589
 590 /*
 591  * Environment Configuration
 592  */
 593 #define CONFIG_ENV_OVERWRITE
 594
 595 #define CONFIG_NETDEV           "eth1"
 596
 597 #define CONFIG_HOSTNAME         "mpc8313erdb"
 598 #define CONFIG_ROOTPATH         "/nfs/root/path"
 599 #define CONFIG_BOOTFILE         "uImage"
 600                                 /* U-Boot image on TFTP server */
 601 #define CONFIG_UBOOTPATH        "u-boot.bin"
 602 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 603
 604                                 /* default location for tftp and bootm */
 605 #define CONFIG_LOADADDR         800000
 606
 607 #define CONFIG_EXTRA_ENV_SETTINGS \
 608         "netdev=" CONFIG_NETDEV "\0"                                    \
 609         "ethprime=TSEC1\0"                                              \
 610         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 611         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 612                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 613                         " +$filesize; " \
 614                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 615                         " +$filesize; " \
 616                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 617                         " $filesize; "  \
 618                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 619                         " +$filesize; " \
 620                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 621                         " $filesize\0"  \
 622         "fdtaddr=780000\0"                                              \
 623         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 624         "console=ttyS0\0"                                               \
 625         "setbootargs=setenv bootargs "                                  \
 626                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 627         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 628                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 629                                                         "$netdev:off " \
 630                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 631
 632 #define CONFIG_NFSBOOTCOMMAND                                           \
 633         "setenv rootdev /dev/nfs;"                                      \
 634         "run setbootargs;"                                              \
 635         "run setipargs;"                                                \
 636         "tftp $loadaddr $bootfile;"                                     \
 637         "tftp $fdtaddr $fdtfile;"                                       \
 638         "bootm $loadaddr - $fdtaddr"
 639
 640 #define CONFIG_RAMBOOTCOMMAND                                           \
 641         "setenv rootdev /dev/ram;"                                      \
 642         "run setbootargs;"                                              \
 643         "tftp $ramdiskaddr $ramdiskfile;"                               \
 644         "tftp $loadaddr $bootfile;"                                     \
 645         "tftp $fdtaddr $fdtfile;"                                       \
 646         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 647
 648 #endif  /* __CONFIG_H */