1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
6 * mpc8313epb board configuration file
13 * High Level Configuration Options
16 #define CONFIG_MPC831x 1
17 #define CONFIG_MPC8313 1
18 #define CONFIG_MPC8313ERDB 1
21 #define CONFIG_SPL_INIT_MINIMAL
22 #define CONFIG_SPL_FLUSH_IMAGE
23 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
24 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
26 #ifdef CONFIG_SPL_BUILD
27 #define CONFIG_NS16550_MIN_FUNCTIONS
30 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
31 #define CONFIG_SPL_MAX_SIZE (4 * 1024)
32 #define CONFIG_SPL_PAD_TO 0x4000
34 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
35 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
36 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
37 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
38 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
39 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
41 #ifdef CONFIG_SPL_BUILD
42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
45 #endif /* CONFIG_NAND */
47 #ifndef CONFIG_SYS_MONITOR_BASE
48 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
51 #define CONFIG_PCI_INDIRECT_BRIDGE
52 #define CONFIG_FSL_ELBC 1
54 #define CONFIG_MISC_INIT_R
62 #define CONFIG_VSC7385_ENET
65 #ifdef CONFIG_SYS_66MHZ
66 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
67 #elif defined(CONFIG_SYS_33MHZ)
68 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
70 #error Unknown oscillator frequency.
73 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
75 #define CONFIG_SYS_IMMR 0xE0000000
77 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
78 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
81 #define CONFIG_SYS_MEMTEST_START 0x00001000
82 #define CONFIG_SYS_MEMTEST_END 0x07f00000
84 /* Early revs of this board will lock up hard when attempting
85 * to access the PMC registers, unless a JTAG debugger is
86 * connected, or some resistor modifications are made.
88 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
90 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
91 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
94 * Device configurations
99 #ifdef CONFIG_VSC7385_ENET
103 /* The flash address and size of the VSC7385 firmware image */
104 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
105 #define CONFIG_VSC7385_IMAGE_SIZE 8192
112 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
113 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
114 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
117 * Manually set up DDR parameters, as this board does not
118 * seem to have the SPD connected to I2C.
120 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
121 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
122 | CSCONFIG_ODT_RD_NEVER \
123 | CSCONFIG_ODT_WR_ONLY_CURRENT \
124 | CSCONFIG_ROW_BIT_13 \
125 | CSCONFIG_COL_BIT_10)
128 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
129 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
130 | (0 << TIMING_CFG0_WRT_SHIFT) \
131 | (0 << TIMING_CFG0_RRT_SHIFT) \
132 | (0 << TIMING_CFG0_WWT_SHIFT) \
133 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
134 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
135 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
136 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
138 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
139 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
140 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
141 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
142 | (10 << TIMING_CFG1_REFREC_SHIFT) \
143 | (3 << TIMING_CFG1_WRREC_SHIFT) \
144 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
145 | (2 << TIMING_CFG1_WRTORD_SHIFT))
147 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
148 | (5 << TIMING_CFG2_CPO_SHIFT) \
149 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
150 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
151 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
152 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
153 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
154 /* 0x129048c6 */ /* P9-45,may need tuning */
155 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
156 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
158 #if defined(CONFIG_DDR_2T_TIMING)
159 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
160 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
165 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
166 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
170 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
171 /* set burst length to 8 for 32-bit data path */
172 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
173 | (0x0632 << SDRAM_MODE_SD_SHIFT))
175 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
177 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
179 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
185 * FLASH on the Local Bus
187 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
188 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
189 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
190 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
191 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
192 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
193 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
195 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
196 | BR_PS_16 /* 16 bit port */ \
197 | BR_MS_GPCM /* MSEL = GPCM */ \
199 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
204 /* 0xFF006FF7 TODO SLOW 16 MB flash size */
205 /* window base at flash base */
206 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
207 /* 16 MB window size */
208 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
210 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
211 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
213 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
214 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
216 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
217 !defined(CONFIG_SPL_BUILD)
218 #define CONFIG_SYS_RAMBOOT
221 #define CONFIG_SYS_INIT_RAM_LOCK 1
222 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
223 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
225 #define CONFIG_SYS_GBL_DATA_OFFSET \
226 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
227 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
229 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
230 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
231 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
234 * Local Bus LCRR and LBCR regs
236 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
237 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
238 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
239 | (0xFF << LBCR_BMT_SHIFT) \
240 | 0xF) /* 0x0004ff0f */
242 /* LB refresh timer prescal, 266MHz/32 */
243 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
245 /* drivers/mtd/nand/nand.c */
246 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
247 #define CONFIG_SYS_NAND_BASE 0xFFF00000
249 #define CONFIG_SYS_NAND_BASE 0xE2800000
252 #define CONFIG_MTD_DEVICE
253 #define CONFIG_MTD_PARTITION
255 #define CONFIG_SYS_MAX_NAND_DEVICE 1
256 #define CONFIG_NAND_FSL_ELBC 1
257 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
258 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
260 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
261 | BR_DECC_CHK_GEN /* Use HW ECC */ \
262 | BR_PS_8 /* 8 bit port */ \
263 | BR_MS_FCM /* MSEL = FCM */ \
265 #define CONFIG_SYS_NAND_OR_PRELIM \
266 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
276 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
277 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
278 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
279 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
281 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
282 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
283 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
284 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
287 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
288 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
290 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
291 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
293 /* local bus write LED / read status buffer (BCSR) mapping */
294 #define CONFIG_SYS_BCSR_ADDR 0xFA000000
295 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
296 /* map at 0xFA000000 on LCS3 */
297 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
298 | BR_PS_8 /* 8 bit port */ \
299 | BR_MS_GPCM /* MSEL = GPCM */ \
302 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
311 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
312 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
316 #ifdef CONFIG_VSC7385_ENET
318 /* VSC7385 Base address on LCS2 */
319 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
320 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
322 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
323 | BR_PS_8 /* 8 bit port */ \
324 | BR_MS_GPCM /* MSEL = GPCM */ \
326 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
336 /* Access window base at VSC7385 base */
337 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
338 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
342 #define CONFIG_MPC83XX_GPIO 1
347 #define CONFIG_SYS_NS16550_SERIAL
348 #define CONFIG_SYS_NS16550_REG_SIZE 1
350 #define CONFIG_SYS_BAUDRATE_TABLE \
351 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
353 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
354 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
357 #define CONFIG_SYS_I2C
358 #define CONFIG_SYS_I2C_FSL
359 #define CONFIG_SYS_FSL_I2C_SPEED 400000
360 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
361 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
362 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
363 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
364 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
365 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
369 * Addresses are mapped 1-1.
371 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
372 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
373 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
374 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
375 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
376 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
377 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
378 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
379 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
381 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
387 #define CONFIG_GMII /* MII PHY management */
390 #define CONFIG_HAS_ETH0
391 #define CONFIG_TSEC1_NAME "TSEC0"
392 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
393 #define TSEC1_PHY_ADDR 0x1c
394 #define TSEC1_FLAGS TSEC_GIGABIT
395 #define TSEC1_PHYIDX 0
399 #define CONFIG_HAS_ETH1
400 #define CONFIG_TSEC2_NAME "TSEC1"
401 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
402 #define TSEC2_PHY_ADDR 4
403 #define TSEC2_FLAGS TSEC_GIGABIT
404 #define TSEC2_PHYIDX 0
407 /* Options are: TSEC[0-1] */
408 #define CONFIG_ETHPRIME "TSEC1"
411 * Configure on-board RTC
413 #define CONFIG_RTC_DS1337
414 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
419 #if defined(CONFIG_NAND)
420 #define CONFIG_ENV_OFFSET (512 * 1024)
421 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
422 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
423 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
424 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
425 #define CONFIG_ENV_OFFSET_REDUND \
426 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
427 #elif !defined(CONFIG_SYS_RAMBOOT)
428 #define CONFIG_ENV_ADDR \
429 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
430 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
431 #define CONFIG_ENV_SIZE 0x2000
433 /* Address and size of Redundant Environment Sector */
435 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
436 #define CONFIG_ENV_SIZE 0x2000
439 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
440 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
445 #define CONFIG_BOOTP_BOOTFILESIZE
448 * Command line configuration.
452 * Miscellaneous configurable options
454 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
455 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
457 /* Boot Argument Buffer Size */
458 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
461 * For booting Linux, the board info and command line data
462 * have to be in the first 256 MB of memory, since this is
463 * the maximum mapped by the Linux kernel during initialization.
465 /* Initial Memory map for Linux*/
466 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
467 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
469 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
471 #ifdef CONFIG_SYS_66MHZ
473 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
475 #define CONFIG_SYS_HRCW_LOW (\
476 0x20000000 /* reserved, must be set */ |\
478 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
479 HRCWL_DDR_TO_SCB_CLK_2X1 |\
480 HRCWL_CSB_TO_CLKIN_2X1 |\
481 HRCWL_CORE_TO_CSB_2X1)
483 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
485 #elif defined(CONFIG_SYS_33MHZ)
487 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
489 #define CONFIG_SYS_HRCW_LOW (\
490 0x20000000 /* reserved, must be set */ |\
492 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
493 HRCWL_DDR_TO_SCB_CLK_2X1 |\
494 HRCWL_CSB_TO_CLKIN_5X1 |\
495 HRCWL_CORE_TO_CSB_2X1)
497 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
501 #define CONFIG_SYS_HRCW_HIGH_BASE (\
503 HRCWH_PCI1_ARBITER_ENABLE |\
505 HRCWH_BOOTSEQ_DISABLE |\
506 HRCWH_SW_WATCHDOG_DISABLE |\
507 HRCWH_TSEC1M_IN_RGMII |\
508 HRCWH_TSEC2M_IN_RGMII |\
512 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
513 HRCWH_FROM_0XFFF00100 |\
514 HRCWH_ROM_LOC_NAND_SP_8BIT |\
517 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
518 HRCWH_FROM_0X00000100 |\
519 HRCWH_ROM_LOC_LOCAL_16BIT |\
523 /* System IO Config */
524 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
525 /* Enable Internal USB Phy and GPIO on LCD Connector */
526 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
528 #define CONFIG_SYS_HID0_INIT 0x000000000
529 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
530 HID0_ENABLE_INSTRUCTION_CACHE | \
531 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
533 #define CONFIG_SYS_HID2 HID2_HBE
535 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
537 /* DDR @ 0x00000000 */
538 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
539 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
544 /* PCI @ 0x80000000 */
545 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
546 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
550 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
552 | BATL_CACHEINHIBIT \
553 | BATL_GUARDEDSTORAGE)
554 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
559 /* PCI2 not supported on 8313 */
560 #define CONFIG_SYS_IBAT3L (0)
561 #define CONFIG_SYS_IBAT3U (0)
562 #define CONFIG_SYS_IBAT4L (0)
563 #define CONFIG_SYS_IBAT4U (0)
565 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
566 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
568 | BATL_CACHEINHIBIT \
569 | BATL_GUARDEDSTORAGE)
570 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
575 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
576 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
577 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
579 #define CONFIG_SYS_IBAT7L (0)
580 #define CONFIG_SYS_IBAT7U (0)
582 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
583 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
584 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
585 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
586 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
587 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
588 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
589 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
590 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
591 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
592 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
593 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
594 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
595 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
596 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
597 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
600 * Environment Configuration
602 #define CONFIG_ENV_OVERWRITE
604 #define CONFIG_NETDEV "eth1"
606 #define CONFIG_HOSTNAME "mpc8313erdb"
607 #define CONFIG_ROOTPATH "/nfs/root/path"
608 #define CONFIG_BOOTFILE "uImage"
609 /* U-Boot image on TFTP server */
610 #define CONFIG_UBOOTPATH "u-boot.bin"
611 #define CONFIG_FDTFILE "mpc8313erdb.dtb"
613 /* default location for tftp and bootm */
614 #define CONFIG_LOADADDR 800000
616 #define CONFIG_EXTRA_ENV_SETTINGS \
617 "netdev=" CONFIG_NETDEV "\0" \
619 "uboot=" CONFIG_UBOOTPATH "\0" \
620 "tftpflash=tftpboot $loadaddr $uboot; " \
621 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
623 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
625 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
627 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
629 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
632 "fdtfile=" CONFIG_FDTFILE "\0" \
634 "setbootargs=setenv bootargs " \
635 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
636 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
637 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
639 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
641 #define CONFIG_NFSBOOTCOMMAND \
642 "setenv rootdev /dev/nfs;" \
645 "tftp $loadaddr $bootfile;" \
646 "tftp $fdtaddr $fdtfile;" \
647 "bootm $loadaddr - $fdtaddr"
649 #define CONFIG_RAMBOOTCOMMAND \
650 "setenv rootdev /dev/ram;" \
652 "tftp $ramdiskaddr $ramdiskfile;" \
653 "tftp $loadaddr $bootfile;" \
654 "tftp $fdtaddr $fdtfile;" \
655 "bootm $loadaddr $ramdiskaddr $fdtaddr"
657 #endif /* __CONFIG_H */