Merge branch 'master' of git://git.denx.de/u-boot-spi
[platform/kernel/u-boot.git] / include / configs / MPC8308RDB.h
1 /*
2  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
3  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4  *
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 #define CONFIG_DISPLAY_BOARDINFO
13
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_E300             1 /* E300 family */
18 #define CONFIG_MPC830x          1 /* MPC830x family */
19 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
20 #define CONFIG_MPC8308RDB       1 /* MPC8308RDB board specific */
21
22 #define CONFIG_SYS_TEXT_BASE    0xFE000000
23
24 #define CONFIG_MISC_INIT_R
25
26 #define CONFIG_MMC     1
27
28 #ifdef CONFIG_MMC
29 #define CONFIG_FSL_ESDHC
30 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
31 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
32 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
33
34 #define CONFIG_CMD_MMC
35 #define CONFIG_GENERIC_MMC
36 #define CONFIG_CMD_FAT
37 #define CONFIG_DOS_PARTITION
38 #endif
39
40 /*
41  * On-board devices
42  *
43  * TSEC1 is SoC TSEC
44  * TSEC2 is VSC switch
45  */
46 #define CONFIG_TSEC1
47 #define CONFIG_VSC7385_ENET
48
49 /*
50  * System Clock Setup
51  */
52 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
53 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
54
55 /*
56  * Hardware Reset Configuration Word
57  * if CLKIN is 66.66MHz, then
58  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
59  * We choose the A type silicon as default, so the core is 400Mhz.
60  */
61 #define CONFIG_SYS_HRCW_LOW (\
62         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
63         HRCWL_DDR_TO_SCB_CLK_2X1 |\
64         HRCWL_SVCOD_DIV_2 |\
65         HRCWL_CSB_TO_CLKIN_4X1 |\
66         HRCWL_CORE_TO_CSB_3X1)
67 /*
68  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
69  * in 8308's HRCWH according to the manual, but original Freescale's
70  * code has them and I've expirienced some problems using the board
71  * with BDI3000 attached when I've tried to set these bits to zero
72  * (UART doesn't work after the 'reset run' command).
73  */
74 #define CONFIG_SYS_HRCW_HIGH (\
75         HRCWH_PCI_HOST |\
76         HRCWH_PCI1_ARBITER_ENABLE |\
77         HRCWH_CORE_ENABLE |\
78         HRCWH_FROM_0X00000100 |\
79         HRCWH_BOOTSEQ_DISABLE |\
80         HRCWH_SW_WATCHDOG_DISABLE |\
81         HRCWH_ROM_LOC_LOCAL_16BIT |\
82         HRCWH_RL_EXT_LEGACY |\
83         HRCWH_TSEC1M_IN_RGMII |\
84         HRCWH_TSEC2M_IN_RGMII |\
85         HRCWH_BIG_ENDIAN)
86
87 /*
88  * System IO Config
89  */
90 #define CONFIG_SYS_SICRH (\
91         SICRH_ESDHC_A_SD |\
92         SICRH_ESDHC_B_SD |\
93         SICRH_ESDHC_C_SD |\
94         SICRH_GPIO_A_TSEC2 |\
95         SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
96         SICRH_IEEE1588_A_GPIO |\
97         SICRH_USB |\
98         SICRH_GTM_GPIO |\
99         SICRH_IEEE1588_B_GPIO |\
100         SICRH_ETSEC2_CRS |\
101         SICRH_GPIOSEL_1 |\
102         SICRH_TMROBI_V3P3 |\
103         SICRH_TSOBI1_V2P5 |\
104         SICRH_TSOBI2_V2P5)      /* 0x01b7d103 */
105 #define CONFIG_SYS_SICRL (\
106         SICRL_SPI_PF0 |\
107         SICRL_UART_PF0 |\
108         SICRL_IRQ_PF0 |\
109         SICRL_I2C2_PF0 |\
110         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000040 */
111
112 /*
113  * IMMR new address
114  */
115 #define CONFIG_SYS_IMMR         0xE0000000
116
117 /*
118  * SERDES
119  */
120 #define CONFIG_FSL_SERDES
121 #define CONFIG_FSL_SERDES1      0xe3000
122
123 /*
124  * Arbiter Setup
125  */
126 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
127 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
128 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
129
130 /*
131  * DDR Setup
132  */
133 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
134 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
135 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
136 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
137 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
138                                 | DDRCDR_PZ_LOZ \
139                                 | DDRCDR_NZ_LOZ \
140                                 | DDRCDR_ODT \
141                                 | DDRCDR_Q_DRN)
142                                 /* 0x7b880001 */
143 /*
144  * Manually set up DDR parameters
145  * consist of two chips HY5PS12621BFP-C4 from HYNIX
146  */
147
148 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
149
150 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
151 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
152                                 | CSCONFIG_ODT_RD_NEVER \
153                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
154                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
155                                 /* 0x80010102 */
156 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
157 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
158                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
159                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
160                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
161                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
162                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
163                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
164                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
165                                 /* 0x00220802 */
166 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
167                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
168                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
169                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
170                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
171                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
172                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
173                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
174                                 /* 0x27256222 */
175 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
176                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
177                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
178                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
179                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
180                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
181                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
182                                 /* 0x121048c5 */
183 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
184                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
185                                 /* 0x03600100 */
186 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
187                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
188                                 | SDRAM_CFG_DBW_32)
189                                 /* 0x43080000 */
190
191 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
192 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
193                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
194                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
195 #define CONFIG_SYS_DDR_MODE2            0x00000000
196
197 /*
198  * Memory test
199  */
200 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
201 #define CONFIG_SYS_MEMTEST_END          0x07f00000
202
203 /*
204  * The reserved memory
205  */
206 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
207
208 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
209 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
210
211 /*
212  * Initial RAM Base Address Setup
213  */
214 #define CONFIG_SYS_INIT_RAM_LOCK        1
215 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
216 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
217 #define CONFIG_SYS_GBL_DATA_OFFSET      \
218         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
219
220 /*
221  * Local Bus Configuration & Clock Setup
222  */
223 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
224 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
225 #define CONFIG_SYS_LBC_LBCR             0x00040000
226
227 /*
228  * FLASH on the Local Bus
229  */
230 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
231 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
232 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
233
234 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
235 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is 8M */
236 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
237
238 /* Window base at flash base */
239 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
240 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
241
242 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
243                                 | BR_PS_16      /* 16 bit port */ \
244                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
245                                 | BR_V)         /* valid */
246 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
247                                 | OR_UPM_XAM \
248                                 | OR_GPCM_CSNT \
249                                 | OR_GPCM_ACS_DIV2 \
250                                 | OR_GPCM_XACS \
251                                 | OR_GPCM_SCY_15 \
252                                 | OR_GPCM_TRLX_SET \
253                                 | OR_GPCM_EHTR_SET)
254
255 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
256 /* 127 64KB sectors and 8 8KB top sectors per device */
257 #define CONFIG_SYS_MAX_FLASH_SECT       135
258
259 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
260 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
261
262 /*
263  * NAND Flash on the Local Bus
264  */
265 #define CONFIG_SYS_NAND_BASE    0xE0600000              /* 0xE0600000 */
266 #define CONFIG_SYS_NAND_WINDOW_SIZE     (32 * 1024)     /* 0x00008000 */
267 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
268                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
269                                 | BR_PS_8               /* 8 bit Port */ \
270                                 | BR_MS_FCM             /* MSEL = FCM */ \
271                                 | BR_V)                 /* valid */
272 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
273                                 | OR_FCM_CSCT \
274                                 | OR_FCM_CST \
275                                 | OR_FCM_CHT \
276                                 | OR_FCM_SCY_1 \
277                                 | OR_FCM_TRLX \
278                                 | OR_FCM_EHTR)
279                                 /* 0xFFFF8396 */
280
281 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
282 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
283
284 #ifdef CONFIG_VSC7385_ENET
285 #define CONFIG_TSEC2
286                                         /* VSC7385 Base address on CS2 */
287 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
288 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024) /* 0x00020000 */
289 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
290                                         | BR_PS_8       /* 8-bit port */ \
291                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
292                                         | BR_V)         /* valid */
293                                         /* 0xF0000801 */
294 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
295                                         | OR_GPCM_CSNT \
296                                         | OR_GPCM_XACS \
297                                         | OR_GPCM_SCY_15 \
298                                         | OR_GPCM_SETA \
299                                         | OR_GPCM_TRLX_SET \
300                                         | OR_GPCM_EHTR_SET)
301                                         /* 0xFFFE09FF */
302 /* Access window base at VSC7385 base */
303 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
304 /* Access window size 128K */
305 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
306 /* The flash address and size of the VSC7385 firmware image */
307 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
308 #define CONFIG_VSC7385_IMAGE_SIZE       8192
309 #endif
310 /*
311  * Serial Port
312  */
313 #define CONFIG_CONS_INDEX       1
314 #define CONFIG_SYS_NS16550_SERIAL
315 #define CONFIG_SYS_NS16550_REG_SIZE     1
316 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
317
318 #define CONFIG_SYS_BAUDRATE_TABLE  \
319         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
320
321 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
322 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
323
324 /* Use the HUSH parser */
325 #define CONFIG_SYS_HUSH_PARSER
326
327 /* Pass open firmware flat tree */
328
329 /* I2C */
330 #define CONFIG_SYS_I2C
331 #define CONFIG_SYS_I2C_FSL
332 #define CONFIG_SYS_FSL_I2C_SPEED        400000
333 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
334 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
335 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
336 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
337 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
338 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
339
340 /*
341  * SPI on header J8
342  *
343  * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
344  * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
345  */
346 #ifdef CONFIG_MPC8XXX_SPI
347 #define CONFIG_CMD_SPI
348 #define CONFIG_USE_SPIFLASH
349 #define CONFIG_CMD_SF
350 #endif
351
352 /*
353  * Board info - revision and where boot from
354  */
355 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
356
357 /*
358  * Config on-board RTC
359  */
360 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
361 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
362
363 /*
364  * General PCI
365  * Addresses are mapped 1-1.
366  */
367 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
368 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
369 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
370 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
371 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
372 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
373 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
374 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
375 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
376
377 /* enable PCIE clock */
378 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
379
380 #define CONFIG_PCI
381 #define CONFIG_PCI_INDIRECT_BRIDGE
382 #define CONFIG_PCIE
383
384 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
385
386 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
387 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
388
389 /*
390  * TSEC
391  */
392 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
393 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
394 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
395 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
396 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
397
398 /*
399  * TSEC ethernet configuration
400  */
401 #define CONFIG_MII              1 /* MII PHY management */
402 #define CONFIG_TSEC1_NAME       "eTSEC0"
403 #define CONFIG_TSEC2_NAME       "eTSEC1"
404 #define TSEC1_PHY_ADDR          2
405 #define TSEC2_PHY_ADDR          1
406 #define TSEC1_PHYIDX            0
407 #define TSEC2_PHYIDX            0
408 #define TSEC1_FLAGS             TSEC_GIGABIT
409 #define TSEC2_FLAGS             TSEC_GIGABIT
410
411 /* Options are: eTSEC[0-1] */
412 #define CONFIG_ETHPRIME         "eTSEC0"
413
414 /*
415  * Environment
416  */
417 #define CONFIG_ENV_IS_IN_FLASH  1
418 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
419                                  CONFIG_SYS_MONITOR_LEN)
420 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
421 #define CONFIG_ENV_SIZE         0x2000
422 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
423 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
424
425 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
426 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
427
428 /*
429  * BOOTP options
430  */
431 #define CONFIG_BOOTP_BOOTFILESIZE
432 #define CONFIG_BOOTP_BOOTPATH
433 #define CONFIG_BOOTP_GATEWAY
434 #define CONFIG_BOOTP_HOSTNAME
435
436 /*
437  * Command line configuration.
438  */
439 #define CONFIG_CMD_DATE
440 #define CONFIG_CMD_DHCP
441 #define CONFIG_CMD_I2C
442 #define CONFIG_CMD_MII
443 #define CONFIG_CMD_PCI
444 #define CONFIG_CMD_PING
445
446 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
447
448 /*
449  * Miscellaneous configurable options
450  */
451 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
452 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
453
454 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
455
456 /* Print Buffer Size */
457 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
458 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
459 /* Boot Argument Buffer Size */
460 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
461
462 /*
463  * For booting Linux, the board info and command line data
464  * have to be in the first 256 MB of memory, since this is
465  * the maximum mapped by the Linux kernel during initialization.
466  */
467 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
468
469 /*
470  * Core HID Setup
471  */
472 #define CONFIG_SYS_HID0_INIT    0x000000000
473 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
474                                  HID0_ENABLE_INSTRUCTION_CACHE | \
475                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
476 #define CONFIG_SYS_HID2         HID2_HBE
477
478 /*
479  * MMU Setup
480  */
481
482 /* DDR: cache cacheable */
483 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
484                                         BATL_MEMCOHERENCE)
485 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
486                                         BATU_VS | BATU_VP)
487 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
488 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
489
490 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
491 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
492                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
493 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
494                                         BATU_VP)
495 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
496 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
497
498 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
499 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
500                                         BATL_MEMCOHERENCE)
501 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
502                                         BATU_VS | BATU_VP)
503 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
504                                         BATL_CACHEINHIBIT | \
505                                         BATL_GUARDEDSTORAGE)
506 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
507
508 /* Stack in dcache: cacheable, no memory coherence */
509 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
510 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
511                                         BATU_VS | BATU_VP)
512 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
513 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
514
515 /*
516  * Environment Configuration
517  */
518
519 #define CONFIG_ENV_OVERWRITE
520
521 #if defined(CONFIG_TSEC_ENET)
522 #define CONFIG_HAS_ETH0
523 #define CONFIG_HAS_ETH1
524 #endif
525
526 #define CONFIG_BAUDRATE 115200
527
528 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
529
530 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
531
532 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
533         "netdev=eth0\0"                                                 \
534         "consoledev=ttyS0\0"                                            \
535         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
536                 "nfsroot=${serverip}:${rootpath}\0"                     \
537         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
538         "addip=setenv bootargs ${bootargs} "                            \
539                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
540                 ":${hostname}:${netdev}:off panic=1\0"                  \
541         "addtty=setenv bootargs ${bootargs}"                            \
542                 " console=${consoledev},${baudrate}\0"                  \
543         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
544         "addmisc=setenv bootargs ${bootargs}\0"                         \
545         "kernel_addr=FE080000\0"                                        \
546         "fdt_addr=FE280000\0"                                           \
547         "ramdisk_addr=FE290000\0"                                       \
548         "u-boot=mpc8308rdb/u-boot.bin\0"                                \
549         "kernel_addr_r=1000000\0"                                       \
550         "fdt_addr_r=C00000\0"                                           \
551         "hostname=mpc8308rdb\0"                                         \
552         "bootfile=mpc8308rdb/uImage\0"                                  \
553         "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"                           \
554         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
555         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
556                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
557         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
558                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
559         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
560                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
561                 "run nfsargs addip addtty addmtd addmisc;"              \
562                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
563         "bootcmd=run flash_self\0"                                      \
564         "load=tftp ${loadaddr} ${u-boot}\0"                             \
565         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
566                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
567                 " +${filesize};cp.b ${fileaddr} "                       \
568                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
569         "upd=run load update\0"                                         \
570
571 #endif  /* __CONFIG_H */