1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
17 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
18 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
28 #define CONFIG_VSC7385_ENET
33 #define CONFIG_FSL_SERDES
34 #define CONFIG_FSL_SERDES1 0xe3000
39 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
40 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
41 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
42 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
43 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
50 * Manually set up DDR parameters
51 * consist of two chips HY5PS12621BFP-C4 from HYNIX
54 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
56 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
57 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
58 | CSCONFIG_ODT_RD_NEVER \
59 | CSCONFIG_ODT_WR_ONLY_CURRENT \
60 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
62 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
63 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
64 | (0 << TIMING_CFG0_WRT_SHIFT) \
65 | (0 << TIMING_CFG0_RRT_SHIFT) \
66 | (0 << TIMING_CFG0_WWT_SHIFT) \
67 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
68 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
69 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
70 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
72 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
73 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
74 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
75 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
76 | (6 << TIMING_CFG1_REFREC_SHIFT) \
77 | (2 << TIMING_CFG1_WRREC_SHIFT) \
78 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
79 | (2 << TIMING_CFG1_WRTORD_SHIFT))
81 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
82 | (4 << TIMING_CFG2_CPO_SHIFT) \
83 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
84 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
85 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
86 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
87 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
89 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
90 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
92 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
93 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
97 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
98 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
99 | (0x0232 << SDRAM_MODE_SD_SHIFT))
100 /* ODT 150ohm CL=3, AL=1 on SDRAM */
101 #define CONFIG_SYS_DDR_MODE2 0x00000000
106 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
107 #define CONFIG_SYS_MEMTEST_END 0x07f00000
110 * The reserved memory
112 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
114 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
115 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
118 * Initial RAM Base Address Setup
120 #define CONFIG_SYS_INIT_RAM_LOCK 1
121 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
122 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
123 #define CONFIG_SYS_GBL_DATA_OFFSET \
124 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
127 * Local Bus Configuration & Clock Setup
129 #define CONFIG_SYS_LBC_LBCR 0x00040000
132 * FLASH on the Local Bus
134 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
136 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
137 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
140 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
141 /* 127 64KB sectors and 8 8KB top sectors per device */
142 #define CONFIG_SYS_MAX_FLASH_SECT 135
144 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
145 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
148 * NAND Flash on the Local Bus
150 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
151 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
154 #ifdef CONFIG_VSC7385_ENET
156 /* VSC7385 Base address on CS2 */
157 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
158 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
160 /* The flash address and size of the VSC7385 firmware image */
161 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
162 #define CONFIG_VSC7385_IMAGE_SIZE 8192
167 #define CONFIG_SYS_NS16550_SERIAL
168 #define CONFIG_SYS_NS16550_REG_SIZE 1
169 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
171 #define CONFIG_SYS_BAUDRATE_TABLE \
172 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
174 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
175 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
178 #define CONFIG_SYS_I2C
179 #define CONFIG_SYS_I2C_FSL
180 #define CONFIG_SYS_FSL_I2C_SPEED 400000
181 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
182 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
183 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
184 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
185 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
186 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
191 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
192 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
194 #ifdef CONFIG_MPC8XXX_SPI
195 #define CONFIG_USE_SPIFLASH
199 * Board info - revision and where boot from
201 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
204 * Config on-board RTC
206 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
207 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
211 * Addresses are mapped 1-1.
213 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
214 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
215 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
216 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
217 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
218 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
219 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
220 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
221 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
223 /* enable PCIE clock */
224 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
226 #define CONFIG_PCI_INDIRECT_BRIDGE
229 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
230 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
235 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
236 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
237 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
238 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
241 * TSEC ethernet configuration
243 #define CONFIG_TSEC1_NAME "eTSEC0"
244 #define CONFIG_TSEC2_NAME "eTSEC1"
245 #define TSEC1_PHY_ADDR 2
246 #define TSEC2_PHY_ADDR 1
247 #define TSEC1_PHYIDX 0
248 #define TSEC2_PHYIDX 0
249 #define TSEC1_FLAGS TSEC_GIGABIT
250 #define TSEC2_FLAGS TSEC_GIGABIT
252 /* Options are: eTSEC[0-1] */
253 #define CONFIG_ETHPRIME "eTSEC0"
258 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
259 CONFIG_SYS_MONITOR_LEN)
260 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
261 #define CONFIG_ENV_SIZE 0x2000
262 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
263 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
265 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
266 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
271 #define CONFIG_BOOTP_BOOTFILESIZE
274 * Command line configuration.
278 * Miscellaneous configurable options
280 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
282 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
284 /* Boot Argument Buffer Size */
285 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
288 * For booting Linux, the board info and command line data
289 * have to be in the first 256 MB of memory, since this is
290 * the maximum mapped by the Linux kernel during initialization.
292 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
293 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
296 * Environment Configuration
299 #define CONFIG_ENV_OVERWRITE
301 #if defined(CONFIG_TSEC_ENET)
302 #define CONFIG_HAS_ETH0
303 #define CONFIG_HAS_ETH1
306 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
309 #define CONFIG_EXTRA_ENV_SETTINGS \
311 "consoledev=ttyS0\0" \
312 "nfsargs=setenv bootargs root=/dev/nfs rw " \
313 "nfsroot=${serverip}:${rootpath}\0" \
314 "ramargs=setenv bootargs root=/dev/ram rw\0" \
315 "addip=setenv bootargs ${bootargs} " \
316 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
317 ":${hostname}:${netdev}:off panic=1\0" \
318 "addtty=setenv bootargs ${bootargs}" \
319 " console=${consoledev},${baudrate}\0" \
320 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
321 "addmisc=setenv bootargs ${bootargs}\0" \
322 "kernel_addr=FE080000\0" \
323 "fdt_addr=FE280000\0" \
324 "ramdisk_addr=FE290000\0" \
325 "u-boot=mpc8308rdb/u-boot.bin\0" \
326 "kernel_addr_r=1000000\0" \
327 "fdt_addr_r=C00000\0" \
328 "hostname=mpc8308rdb\0" \
329 "bootfile=mpc8308rdb/uImage\0" \
330 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
331 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
332 "flash_self=run ramargs addip addtty addmtd addmisc;" \
333 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
334 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
335 "bootm ${kernel_addr} - ${fdt_addr}\0" \
336 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
337 "tftp ${fdt_addr_r} ${fdtfile};" \
338 "run nfsargs addip addtty addmtd addmisc;" \
339 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
340 "bootcmd=run flash_self\0" \
341 "load=tftp ${loadaddr} ${u-boot}\0" \
342 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
343 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
344 " +${filesize};cp.b ${fileaddr} " \
345 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
346 "upd=run load update\0" \
348 #endif /* __CONFIG_H */