Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
[platform/kernel/u-boot.git] / include / configs / MPC8308RDB.h
1 /*
2  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
3  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4  *
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24
25 #ifndef __CONFIG_H
26 #define __CONFIG_H
27
28 /*
29  * High Level Configuration Options
30  */
31 #define CONFIG_E300             1 /* E300 family */
32 #define CONFIG_MPC83xx          1 /* MPC83xx family */
33 #define CONFIG_MPC830x          1 /* MPC830x family */
34 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
35 #define CONFIG_MPC8308RDB       1 /* MPC8308RDB board specific */
36
37 #define CONFIG_SYS_TEXT_BASE    0xFE000000
38
39 #define CONFIG_MISC_INIT_R
40
41 /* new uImage format support */
42 #define CONFIG_FIT                      1
43 #define CONFIG_FIT_VERBOSE              1
44
45 #define CONFIG_MMC     1
46
47 #ifdef CONFIG_MMC
48 #define CONFIG_FSL_ESDHC
49 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
50 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
51 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
52
53 #define CONFIG_CMD_MMC
54 #define CONFIG_GENERIC_MMC
55 #define CONFIG_CMD_FAT
56 #define CONFIG_DOS_PARTITION
57 #endif
58
59 /*
60  * On-board devices
61  *
62  * TSEC1 is SoC TSEC
63  * TSEC2 is VSC switch
64  */
65 #define CONFIG_TSEC1
66 #define CONFIG_VSC7385_ENET
67
68 /*
69  * System Clock Setup
70  */
71 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
72 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
73
74 /*
75  * Hardware Reset Configuration Word
76  * if CLKIN is 66.66MHz, then
77  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
78  * We choose the A type silicon as default, so the core is 400Mhz.
79  */
80 #define CONFIG_SYS_HRCW_LOW (\
81         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
82         HRCWL_DDR_TO_SCB_CLK_2X1 |\
83         HRCWL_SVCOD_DIV_2 |\
84         HRCWL_CSB_TO_CLKIN_4X1 |\
85         HRCWL_CORE_TO_CSB_3X1)
86 /*
87  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
88  * in 8308's HRCWH according to the manual, but original Freescale's
89  * code has them and I've expirienced some problems using the board
90  * with BDI3000 attached when I've tried to set these bits to zero
91  * (UART doesn't work after the 'reset run' command).
92  */
93 #define CONFIG_SYS_HRCW_HIGH (\
94         HRCWH_PCI_HOST |\
95         HRCWH_PCI1_ARBITER_ENABLE |\
96         HRCWH_CORE_ENABLE |\
97         HRCWH_FROM_0X00000100 |\
98         HRCWH_BOOTSEQ_DISABLE |\
99         HRCWH_SW_WATCHDOG_DISABLE |\
100         HRCWH_ROM_LOC_LOCAL_16BIT |\
101         HRCWH_RL_EXT_LEGACY |\
102         HRCWH_TSEC1M_IN_RGMII |\
103         HRCWH_TSEC2M_IN_RGMII |\
104         HRCWH_BIG_ENDIAN)
105
106 /*
107  * System IO Config
108  */
109 #define CONFIG_SYS_SICRH (\
110         SICRH_ESDHC_A_SD |\
111         SICRH_ESDHC_B_SD |\
112         SICRH_ESDHC_C_SD |\
113         SICRH_GPIO_A_TSEC2 |\
114         SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
115         SICRH_IEEE1588_A_GPIO |\
116         SICRH_USB |\
117         SICRH_GTM_GPIO |\
118         SICRH_IEEE1588_B_GPIO |\
119         SICRH_ETSEC2_CRS |\
120         SICRH_GPIOSEL_1 |\
121         SICRH_TMROBI_V3P3 |\
122         SICRH_TSOBI1_V2P5 |\
123         SICRH_TSOBI2_V2P5)      /* 0x01b7d103 */
124 #define CONFIG_SYS_SICRL (\
125         SICRL_SPI_PF0 |\
126         SICRL_UART_PF0 |\
127         SICRL_IRQ_PF0 |\
128         SICRL_I2C2_PF0 |\
129         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000040 */
130
131 /*
132  * IMMR new address
133  */
134 #define CONFIG_SYS_IMMR         0xE0000000
135
136 /*
137  * SERDES
138  */
139 #define CONFIG_FSL_SERDES
140 #define CONFIG_FSL_SERDES1      0xe3000
141
142 /*
143  * Arbiter Setup
144  */
145 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
146 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
147 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
148
149 /*
150  * DDR Setup
151  */
152 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
153 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
154 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
155 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
156 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
157                                 | DDRCDR_PZ_LOZ \
158                                 | DDRCDR_NZ_LOZ \
159                                 | DDRCDR_ODT \
160                                 | DDRCDR_Q_DRN)
161                                 /* 0x7b880001 */
162 /*
163  * Manually set up DDR parameters
164  * consist of two chips HY5PS12621BFP-C4 from HYNIX
165  */
166
167 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
168
169 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
170 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
171                                 | CSCONFIG_ODT_RD_NEVER \
172                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
173                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
174                                 /* 0x80010102 */
175 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
176 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
177                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
178                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
179                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
180                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
181                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
182                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
183                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
184                                 /* 0x00220802 */
185 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
186                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
187                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
188                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
189                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
190                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
191                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
192                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
193                                 /* 0x27256222 */
194 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
195                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
196                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
197                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
198                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
199                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
200                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
201                                 /* 0x121048c5 */
202 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
203                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
204                                 /* 0x03600100 */
205 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
206                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
207                                 | SDRAM_CFG_DBW_32)
208                                 /* 0x43080000 */
209
210 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
211 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
212                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
213                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
214 #define CONFIG_SYS_DDR_MODE2            0x00000000
215
216 /*
217  * Memory test
218  */
219 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
220 #define CONFIG_SYS_MEMTEST_END          0x07f00000
221
222 /*
223  * The reserved memory
224  */
225 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
226
227 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
228 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
229
230 /*
231  * Initial RAM Base Address Setup
232  */
233 #define CONFIG_SYS_INIT_RAM_LOCK        1
234 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
235 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
236 #define CONFIG_SYS_GBL_DATA_OFFSET      \
237         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
238
239 /*
240  * Local Bus Configuration & Clock Setup
241  */
242 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
243 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
244 #define CONFIG_SYS_LBC_LBCR             0x00040000
245
246 /*
247  * FLASH on the Local Bus
248  */
249 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
250 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
251 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
252
253 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
254 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is 8M */
255 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
256
257 /* Window base at flash base */
258 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
259 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
260
261 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
262                                 | BR_PS_16      /* 16 bit port */ \
263                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
264                                 | BR_V)         /* valid */
265 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
266                                 | OR_UPM_XAM \
267                                 | OR_GPCM_CSNT \
268                                 | OR_GPCM_ACS_DIV2 \
269                                 | OR_GPCM_XACS \
270                                 | OR_GPCM_SCY_15 \
271                                 | OR_GPCM_TRLX_SET \
272                                 | OR_GPCM_EHTR_SET)
273
274 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
275 /* 127 64KB sectors and 8 8KB top sectors per device */
276 #define CONFIG_SYS_MAX_FLASH_SECT       135
277
278 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
279 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
280
281 /*
282  * NAND Flash on the Local Bus
283  */
284 #define CONFIG_SYS_NAND_BASE    0xE0600000              /* 0xE0600000 */
285 #define CONFIG_SYS_NAND_WINDOW_SIZE     (32 * 1024)     /* 0x00008000 */
286 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
287                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
288                                 | BR_PS_8               /* 8 bit Port */ \
289                                 | BR_MS_FCM             /* MSEL = FCM */ \
290                                 | BR_V)                 /* valid */
291 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
292                                 | OR_FCM_CSCT \
293                                 | OR_FCM_CST \
294                                 | OR_FCM_CHT \
295                                 | OR_FCM_SCY_1 \
296                                 | OR_FCM_TRLX \
297                                 | OR_FCM_EHTR)
298                                 /* 0xFFFF8396 */
299
300 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
301 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
302
303 #ifdef CONFIG_VSC7385_ENET
304 #define CONFIG_TSEC2
305                                         /* VSC7385 Base address on CS2 */
306 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
307 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024) /* 0x00020000 */
308 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
309                                         | BR_PS_8       /* 8-bit port */ \
310                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
311                                         | BR_V)         /* valid */
312                                         /* 0xF0000801 */
313 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
314                                         | OR_GPCM_CSNT \
315                                         | OR_GPCM_XACS \
316                                         | OR_GPCM_SCY_15 \
317                                         | OR_GPCM_SETA \
318                                         | OR_GPCM_TRLX_SET \
319                                         | OR_GPCM_EHTR_SET)
320                                         /* 0xFFFE09FF */
321 /* Access window base at VSC7385 base */
322 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
323 /* Access window size 128K */
324 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
325 /* The flash address and size of the VSC7385 firmware image */
326 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
327 #define CONFIG_VSC7385_IMAGE_SIZE       8192
328 #endif
329 /*
330  * Serial Port
331  */
332 #define CONFIG_CONS_INDEX       1
333 #define CONFIG_SYS_NS16550
334 #define CONFIG_SYS_NS16550_SERIAL
335 #define CONFIG_SYS_NS16550_REG_SIZE     1
336 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
337
338 #define CONFIG_SYS_BAUDRATE_TABLE  \
339         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
340
341 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
342 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
343
344 /* Use the HUSH parser */
345 #define CONFIG_SYS_HUSH_PARSER
346
347 /* Pass open firmware flat tree */
348 #define CONFIG_OF_LIBFDT        1
349 #define CONFIG_OF_BOARD_SETUP   1
350 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
351
352 /* I2C */
353 #define CONFIG_HARD_I2C         /* I2C with hardware support */
354 #define CONFIG_FSL_I2C
355 #define CONFIG_I2C_MULTI_BUS
356 #define CONFIG_SYS_I2C_SPEED    400000 /* I2C speed and slave address */
357 #define CONFIG_SYS_I2C_SLAVE    0x7F
358 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } /* Don't probe these addrs */
359 #define CONFIG_SYS_I2C_OFFSET   0x3000
360 #define CONFIG_SYS_I2C2_OFFSET  0x3100
361
362 /*
363  * SPI on header J8
364  *
365  * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
366  * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
367  */
368 #ifdef CONFIG_MPC8XXX_SPI
369 #define CONFIG_CMD_SPI
370 #define CONFIG_USE_SPIFLASH
371 #define CONFIG_SPI_FLASH
372 #define CONFIG_SPI_FLASH_SPANSION
373 #define CONFIG_CMD_SF
374 #endif
375
376 /*
377  * Board info - revision and where boot from
378  */
379 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
380
381 /*
382  * Config on-board RTC
383  */
384 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
385 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
386
387 /*
388  * General PCI
389  * Addresses are mapped 1-1.
390  */
391 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
392 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
393 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
394 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
395 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
396 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
397 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
398 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
399 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
400
401 /* enable PCIE clock */
402 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
403
404 #define CONFIG_PCI
405 #define CONFIG_PCIE
406
407 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
408
409 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
410 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
411
412 /*
413  * TSEC
414  */
415 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
416 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
417 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
418 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
419 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
420
421 /*
422  * TSEC ethernet configuration
423  */
424 #define CONFIG_MII              1 /* MII PHY management */
425 #define CONFIG_TSEC1_NAME       "eTSEC0"
426 #define CONFIG_TSEC2_NAME       "eTSEC1"
427 #define TSEC1_PHY_ADDR          2
428 #define TSEC2_PHY_ADDR          1
429 #define TSEC1_PHYIDX            0
430 #define TSEC2_PHYIDX            0
431 #define TSEC1_FLAGS             TSEC_GIGABIT
432 #define TSEC2_FLAGS             TSEC_GIGABIT
433
434 /* Options are: eTSEC[0-1] */
435 #define CONFIG_ETHPRIME         "eTSEC0"
436
437 /*
438  * Environment
439  */
440 #define CONFIG_ENV_IS_IN_FLASH  1
441 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
442                                  CONFIG_SYS_MONITOR_LEN)
443 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
444 #define CONFIG_ENV_SIZE         0x2000
445 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
446 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
447
448 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
449 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
450
451 /*
452  * BOOTP options
453  */
454 #define CONFIG_BOOTP_BOOTFILESIZE
455 #define CONFIG_BOOTP_BOOTPATH
456 #define CONFIG_BOOTP_GATEWAY
457 #define CONFIG_BOOTP_HOSTNAME
458
459 /*
460  * Command line configuration.
461  */
462 #include <config_cmd_default.h>
463
464 #define CONFIG_CMD_DATE
465 #define CONFIG_CMD_DHCP
466 #define CONFIG_CMD_I2C
467 #define CONFIG_CMD_MII
468 #define CONFIG_CMD_NET
469 #define CONFIG_CMD_PCI
470 #define CONFIG_CMD_PING
471
472 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
473
474 /*
475  * Miscellaneous configurable options
476  */
477 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
478 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
479 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
480
481 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
482
483 /* Print Buffer Size */
484 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
485 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
486 /* Boot Argument Buffer Size */
487 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
488 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
489
490 /*
491  * For booting Linux, the board info and command line data
492  * have to be in the first 256 MB of memory, since this is
493  * the maximum mapped by the Linux kernel during initialization.
494  */
495 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
496
497 /*
498  * Core HID Setup
499  */
500 #define CONFIG_SYS_HID0_INIT    0x000000000
501 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
502                                  HID0_ENABLE_INSTRUCTION_CACHE | \
503                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
504 #define CONFIG_SYS_HID2         HID2_HBE
505
506 /*
507  * MMU Setup
508  */
509
510 /* DDR: cache cacheable */
511 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
512                                         BATL_MEMCOHERENCE)
513 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
514                                         BATU_VS | BATU_VP)
515 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
516 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
517
518 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
519 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
520                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
521 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
522                                         BATU_VP)
523 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
524 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
525
526 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
527 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
528                                         BATL_MEMCOHERENCE)
529 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
530                                         BATU_VS | BATU_VP)
531 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
532                                         BATL_CACHEINHIBIT | \
533                                         BATL_GUARDEDSTORAGE)
534 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
535
536 /* Stack in dcache: cacheable, no memory coherence */
537 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
538 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
539                                         BATU_VS | BATU_VP)
540 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
541 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
542
543 /*
544  * Environment Configuration
545  */
546
547 #define CONFIG_ENV_OVERWRITE
548
549 #if defined(CONFIG_TSEC_ENET)
550 #define CONFIG_HAS_ETH0
551 #define CONFIG_HAS_ETH1
552 #endif
553
554 #define CONFIG_BAUDRATE 115200
555
556 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
557
558 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
559
560 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
561         "netdev=eth0\0"                                                 \
562         "consoledev=ttyS0\0"                                            \
563         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
564                 "nfsroot=${serverip}:${rootpath}\0"                     \
565         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
566         "addip=setenv bootargs ${bootargs} "                            \
567                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
568                 ":${hostname}:${netdev}:off panic=1\0"                  \
569         "addtty=setenv bootargs ${bootargs}"                            \
570                 " console=${consoledev},${baudrate}\0"                  \
571         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
572         "addmisc=setenv bootargs ${bootargs}\0"                         \
573         "kernel_addr=FE080000\0"                                        \
574         "fdt_addr=FE280000\0"                                           \
575         "ramdisk_addr=FE290000\0"                                       \
576         "u-boot=mpc8308rdb/u-boot.bin\0"                                \
577         "kernel_addr_r=1000000\0"                                       \
578         "fdt_addr_r=C00000\0"                                           \
579         "hostname=mpc8308rdb\0"                                         \
580         "bootfile=mpc8308rdb/uImage\0"                                  \
581         "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"                           \
582         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
583         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
584                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
585         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
586                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
587         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
588                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
589                 "run nfsargs addip addtty addmtd addmisc;"              \
590                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
591         "bootcmd=run flash_self\0"                                      \
592         "load=tftp ${loadaddr} ${u-boot}\0"                             \
593         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
594                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
595                 " +${filesize};cp.b ${fileaddr} "                       \
596                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
597         "upd=run load update\0"                                         \
598
599 #endif  /* __CONFIG_H */