3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual.
7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
10 * (C) Copyright 2003 Arabella Software Ltd.
11 * Yuli Barcohen <yuli@arabellasw.com>
12 * Added support for SDRAM DIMMs SPD EEPROM, MII.
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 * High Level Configuration Options
41 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
42 #define CONFIG_MPC8260ADS 1 /* ...on motorola ads board */
44 #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
46 /* allow serial and ethaddr to be overwritten */
47 #define CONFIG_ENV_OVERWRITE
50 * select serial console configuration
52 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
53 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
56 * if CONFIG_CONS_NONE is defined, then the serial console routines must
57 * defined elsewhere (for example, on the cogent platform, there are serial
58 * ports on the motherboard which are used for the serial console - see
59 * cogent/cma101/serial.[ch]).
61 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
62 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
63 #undef CONFIG_CONS_NONE /* define if console on something else */
64 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
67 * select ethernet configuration
69 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
70 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
73 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
74 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
75 * from CONFIG_COMMANDS to remove support for networking.
77 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
78 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
79 #undef CONFIG_ETHER_NONE /* define if ether on something else */
81 #ifdef CONFIG_ETHER_ON_FCC
83 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
85 #if (CONFIG_ETHER_INDEX == 2)
89 * - Select bus for bd/buffers (see 28-13)
92 # define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
93 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
94 # define CFG_CPMFCR_RAMTYPE 0
95 # define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
97 #endif /* CONFIG_ETHER_INDEX */
99 #define CONFIG_MII /* MII PHY management */
100 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
102 * GPIO pins used for bit-banged MII communications
104 #define MDIO_PORT 2 /* Port C */
105 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
106 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
107 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
109 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
110 else iop->pdat &= ~0x00400000
112 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
113 else iop->pdat &= ~0x00200000
115 #define MIIDELAY udelay(1)
117 #endif /* CONFIG_ETHER_ON_FCC */
120 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
121 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
122 #define CFG_I2C_SLAVE 0x7F
124 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
125 #define CONFIG_SPD_ADDR 0x50
128 #ifndef CONFIG_SDRAM_PBI
129 #define CONFIG_SDRAM_PBI 1 /* By default, use page-based interleaving */
132 #ifndef CONFIG_8260_CLKIN
133 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
135 #define CONFIG_BAUDRATE 115200
137 #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
161 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
162 #include <cmd_confdefs.h>
165 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
166 #define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
167 #define CONFIG_BOOTARGS "root=/dev/ram rw"
169 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
170 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
171 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
172 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
173 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
174 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
177 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
180 * Miscellaneous configurable options
182 #define CFG_LONGHELP /* undef to save memory */
183 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
184 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
185 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
187 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
189 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
190 #define CFG_MAXARGS 16 /* max number of command args */
191 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
193 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
194 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
196 #define CFG_LOAD_ADDR 0x100000 /* default load address */
198 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
202 #define CFG_FLASH_BASE 0xff800000
203 #define FLASH_BASE 0xff800000
204 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
205 #define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
206 #define CFG_FLASH_SIZE 8
207 #define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
208 #define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
210 /* this is stuff came out of the Motorola docs */
211 #define CFG_DEFAULT_IMMR 0x0F010000
213 #define CFG_IMMR 0xF0000000
214 #define CFG_BCSR 0x04500000
215 #define CFG_SDRAM_BASE 0x00000000
216 #define CFG_LSDRAM_BASE 0x04000000
218 #define RS232EN_1 0x02000002
219 #define RS232EN_2 0x01000001
220 #define FETHIEN 0x08000008
221 #define FETH_RST 0x04000004
223 #define CFG_INIT_RAM_ADDR CFG_IMMR
224 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
225 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
226 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
227 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
231 #define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
232 ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
233 ( HRCW_BMS | HRCW_APPC10 ) |\
234 ( HRCW_MODCK_H0101 ) \
238 #define CFG_HRCW_SLAVE1 0
239 #define CFG_HRCW_SLAVE2 0
240 #define CFG_HRCW_SLAVE3 0
241 #define CFG_HRCW_SLAVE4 0
242 #define CFG_HRCW_SLAVE5 0
243 #define CFG_HRCW_SLAVE6 0
244 #define CFG_HRCW_SLAVE7 0
246 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
247 #define BOOTFLAG_WARM 0x02 /* Software reboot */
249 #define CFG_MONITOR_BASE TEXT_BASE
250 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
254 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
255 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
256 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
259 # define CFG_ENV_IS_IN_FLASH 1
260 # define CFG_ENV_SECT_SIZE 0x40000
261 # define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
263 # define CFG_ENV_IS_IN_NVRAM 1
264 # define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
265 # define CFG_ENV_SIZE 0x200
266 #endif /* CFG_RAMBOOT */
269 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
270 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
271 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
275 #define CFG_HID0_INIT 0
276 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
280 #define CFG_SYPCR 0xFFFFFFC3
281 #define CFG_BCR 0x100C0000
282 #define CFG_SIUMCR 0x0A200000
283 #define CFG_SCCR 0x00000000
284 #define CFG_BR0_PRELIM 0xFF801801
285 #define CFG_OR0_PRELIM 0xFF800836
286 #define CFG_BR1_PRELIM 0x04501801
287 #define CFG_OR1_PRELIM 0xFFFF8010
290 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
291 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
293 #define CFG_PSDMR 0x016EB452
294 #define CFG_MPTPR 0x00001900
295 #define CFG_PSRT 0x00000021
297 #define CFG_RESET_ADDRESS 0x04400000
299 #endif /* __CONFIG_H */