3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual.
7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
10 * (C) Copyright 2003-2004 Arabella Software Ltd.
11 * Yuli Barcohen <yuli@arabellasw.com>
12 * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
13 * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
14 * Ported to MPC8272ADS board.
16 * Copyright (c) 2005 MontaVista Software, Inc.
17 * Vitaly Bordug <vbordug@ru.mvista.com>
18 * Added support for PCI bridge on MPC8272ADS
20 * See file CREDITS for list of people who contributed to this
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License as
25 * published by the Free Software Foundation; either version 2 of
26 * the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
43 * High Level Configuration Options
47 #define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
49 #define CONFIG_CPM2 1 /* Has a CPM2 */
52 * Figure out if we are booting low via flash HRCW or high via the BCSR.
54 #if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
55 # define CFG_LOWBOOT 1
59 #define CFG_8260ADS 1 /* MPC8260ADS */
60 #define CFG_8266ADS 2 /* MPC8266ADS */
61 #define CFG_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
62 #define CFG_8272ADS 4 /* MPC8272ADS */
64 #ifndef CONFIG_ADSTYPE
65 #define CONFIG_ADSTYPE CFG_8260ADS
66 #endif /* CONFIG_ADSTYPE */
68 #if CONFIG_ADSTYPE == CFG_8272ADS
69 #define CONFIG_MPC8272 1
71 #define CONFIG_MPC8260 1
72 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
74 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
76 /* allow serial and ethaddr to be overwritten */
77 #define CONFIG_ENV_OVERWRITE
80 * select serial console configuration
82 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
83 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
86 * if CONFIG_CONS_NONE is defined, then the serial console routines must
87 * defined elsewhere (for example, on the cogent platform, there are serial
88 * ports on the motherboard which are used for the serial console - see
89 * cogent/cma101/serial.[ch]).
91 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
92 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
93 #undef CONFIG_CONS_NONE /* define if console on something else */
94 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
97 * select ethernet configuration
99 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
100 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
103 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
104 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
105 * from CONFIG_COMMANDS to remove support for networking.
107 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
108 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
109 #undef CONFIG_ETHER_NONE /* define if ether on something else */
111 #ifdef CONFIG_ETHER_ON_FCC
113 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
115 #if CONFIG_ETHER_INDEX == 1
117 # define CFG_PHY_ADDR 0
118 # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
119 # define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
121 #elif CONFIG_ETHER_INDEX == 2
123 #if CONFIG_ADSTYPE == CFG_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
124 # define CFG_PHY_ADDR 3
125 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
126 #else /* RxCLK is CLK13, TxCLK is CLK14 */
127 # define CFG_PHY_ADDR 0
128 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
129 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
131 # define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
133 #endif /* CONFIG_ETHER_INDEX */
135 #define CFG_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
136 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */
138 #define CONFIG_MII /* MII PHY management */
139 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
141 * GPIO pins used for bit-banged MII communications
143 #define MDIO_PORT 2 /* Port C */
145 #if CONFIG_ADSTYPE == CFG_8272ADS
146 #define CFG_MDIO_PIN 0x00002000 /* PC18 */
147 #define CFG_MDC_PIN 0x00001000 /* PC19 */
149 #define CFG_MDIO_PIN 0x00400000 /* PC9 */
150 #define CFG_MDC_PIN 0x00200000 /* PC10 */
151 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
153 #define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
154 #define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
155 #define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
157 #define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
158 else iop->pdat &= ~CFG_MDIO_PIN
160 #define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
161 else iop->pdat &= ~CFG_MDC_PIN
163 #define MIIDELAY udelay(1)
165 #endif /* CONFIG_ETHER_ON_FCC */
167 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
168 #undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
170 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
171 #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
172 #define CFG_I2C_SLAVE 0x7F
174 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
175 #define CONFIG_SPD_ADDR 0x50
177 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
180 #ifdef CONFIG_MPC8272
182 #define CONFIG_PCI_PNP
183 #define CONFIG_PCI_BOOTDELAY 0
184 #define CONFIG_PCI_SCAN_SHOW
187 #ifndef CONFIG_SDRAM_PBI
188 #define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
191 #ifndef CONFIG_8260_CLKIN
192 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
193 #define CONFIG_8260_CLKIN 100000000 /* in Hz */
195 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
199 #define CONFIG_BAUDRATE 115200
202 * Command line configuration.
204 #include <config_cmd_all.h>
206 #undef CONFIG_CMD_BEDBUG
207 #undef CONFIG_CMD_BMP
208 #undef CONFIG_CMD_BSP
209 #undef CONFIG_CMD_DATE
210 #undef CONFIG_CMD_DISPLAY
211 #undef CONFIG_CMD_DOC
212 #undef CONFIG_CMD_DTT
213 #undef CONFIG_CMD_EEPROM
214 #undef CONFIG_CMD_ELF
215 #undef CONFIG_CMD_EXT2
216 #undef CONFIG_CMD_FAT
217 #undef CONFIG_CMD_FDC
218 #undef CONFIG_CMD_FDOS
219 #undef CONFIG_CMD_HWFLOW
220 #undef CONFIG_CMD_IDE
221 #undef CONFIG_CMD_KGDB
222 #undef CONFIG_CMD_MMC
223 #undef CONFIG_CMD_NAND
224 #undef CONFIG_CMD_PCMCIA
225 #undef CONFIG_CMD_REISER
226 #undef CONFIG_CMD_SCSI
227 #undef CONFIG_CMD_SPI
228 #undef CONFIG_CMD_SNTP
229 #undef CONFIG_CMD_UNIVERSE
230 #undef CONFIG_CMD_USB
231 #undef CONFIG_CMD_VFD
232 #undef CONFIG_CMD_XIMG
234 #if CONFIG_ADSTYPE == CFG_8272ADS
235 #undef CONFIG_CMD_SDRAM
236 #undef CONFIG_CMD_I2C
238 #elif CONFIG_ADSTYPE >= CFG_PQ2FADS
239 #undef CONFIG_CMD_SDRAM
240 #undef CONFIG_CMD_I2C
241 #undef CONFIG_CMD_PCI
244 #undef CONFIG_CMD_PCI
246 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
251 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
252 #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
253 #define CONFIG_BOOTARGS "root=/dev/mtdblock2"
255 #if defined(CONFIG_CMD_KGDB)
256 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
257 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
258 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
259 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
260 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
263 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
264 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
267 * Miscellaneous configurable options
269 #define CFG_HUSH_PARSER
270 #define CFG_PROMPT_HUSH_PS2 "> "
271 #define CFG_LONGHELP /* undef to save memory */
272 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
273 #if defined(CONFIG & CFG_CMD_KGDB)
274 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
276 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
278 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
279 #define CFG_MAXARGS 16 /* max number of command args */
280 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
282 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
283 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
285 #define CFG_LOAD_ADDR 0x400000 /* default load address */
287 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
289 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
291 #define CFG_FLASH_BASE 0xff800000
292 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
293 #define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
294 #define CFG_FLASH_SIZE 8
295 #define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
296 #define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
297 #define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
298 #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
299 #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
304 * Note: fake mtd_id used, no linux mtd map file
306 #define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
307 #define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
308 #define CFG_JFFS2_SORT_FRAGMENTS
310 /* this is stuff came out of the Motorola docs */
312 #define CFG_DEFAULT_IMMR 0x0F010000
315 #define CFG_IMMR 0xF0000000
316 #define CFG_BCSR 0xF4500000
317 #if CONFIG_ADSTYPE == CFG_8272ADS
318 #define CFG_PCI_INT 0xF8200000
320 #define CFG_SDRAM_BASE 0x00000000
321 #define CFG_LSDRAM_BASE 0xFD000000
323 #define RS232EN_1 0x02000002
324 #define RS232EN_2 0x01000001
325 #define FETHIEN1 0x08000008
326 #define FETH1_RST 0x04000004
327 #define FETHIEN2 0x10000000
328 #define FETH2_RST 0x08000000
329 #define BCSR_PCI_MODE 0x01000000
331 #define CFG_INIT_RAM_ADDR CFG_IMMR
332 #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
333 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
334 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
335 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
338 /* PQ2FADS flash HRCW = 0x0EB4B645 */
339 #define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
340 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
341 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
342 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
345 /* PQ2FADS BCSR HRCW = 0x0CB23645 */
346 #define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
347 ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
348 ( HRCW_BMS | HRCW_APPC10 ) |\
349 ( HRCW_MODCK_H0101 ) \
353 #define CFG_HRCW_SLAVE1 0
354 #define CFG_HRCW_SLAVE2 0
355 #define CFG_HRCW_SLAVE3 0
356 #define CFG_HRCW_SLAVE4 0
357 #define CFG_HRCW_SLAVE5 0
358 #define CFG_HRCW_SLAVE6 0
359 #define CFG_HRCW_SLAVE7 0
361 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
362 #define BOOTFLAG_WARM 0x02 /* Software reboot */
364 #define CFG_MONITOR_BASE TEXT_BASE
365 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
369 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
370 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
373 #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
375 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
376 #endif /* CONFIG_BZIP2 */
379 # define CFG_ENV_IS_IN_FLASH 1
380 # define CFG_ENV_SECT_SIZE 0x40000
381 # define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
383 # define CFG_ENV_IS_IN_NVRAM 1
384 # define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
385 # define CFG_ENV_SIZE 0x200
386 #endif /* CFG_RAMBOOT */
388 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
389 #if defined(CONFIG_CMD_KGDB)
390 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
393 #define CFG_HID0_INIT 0
394 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
398 #define CFG_SYPCR 0xFFFFFFC3
399 #define CFG_BCR 0x100C0000
400 #define CFG_SIUMCR 0x0A200000
401 #define CFG_SCCR SCCR_DFBRG01
402 #define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00001801
403 #define CFG_OR0_PRELIM 0xFF800876
404 #define CFG_BR1_PRELIM CFG_BCSR | 0x00001801
405 #define CFG_OR1_PRELIM 0xFFFF8010
407 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
409 #if CONFIG_ADSTYPE == CFG_8272ADS
410 #define CFG_BR3_PRELIM (CFG_PCI_INT | 0x1801) /* PCI interrupt controller */
411 #define CFG_OR3_PRELIM 0xFFFF8010
414 #define CFG_RMR RMR_CSRE
415 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
416 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
419 #if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS)
420 #undef CFG_LSDRAM_BASE /* No local bus SDRAM on these boards */
421 #endif /* CONFIG_ADSTYPE == CFG_8266ADS */
423 #if CONFIG_ADSTYPE == CFG_PQ2FADS
424 #define CFG_OR2 0xFE002EC0
425 #define CFG_PSDMR 0x824B36A3
426 #define CFG_PSRT 0x13
427 #define CFG_LSDMR 0x828737A3
428 #define CFG_LSRT 0x13
429 #define CFG_MPTPR 0x2800
430 #elif CONFIG_ADSTYPE == CFG_8272ADS
431 #define CFG_OR2 0xFC002CC0
432 #define CFG_PSDMR 0x834E24A3
433 #define CFG_PSRT 0x13
434 #define CFG_MPTPR 0x2800
436 #define CFG_OR2 0xFF000CA0
437 #define CFG_PSDMR 0x016EB452
438 #define CFG_PSRT 0x21
439 #define CFG_LSDMR 0x0086A522
440 #define CFG_LSRT 0x21
441 #define CFG_MPTPR 0x1900
442 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
444 #define CFG_RESET_ADDRESS 0x04400000
446 #if CONFIG_ADSTYPE == CFG_8272ADS
448 /* PCI Memory map (if different from default map */
449 #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
450 #define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
451 #define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
455 * These are the windows that allow the CPU to access PCI address space.
456 * All three PCI master windows, which allow the CPU to access PCI
457 * prefetch, non prefetch, and IO space (see below), must all fit within
462 * Master window that allows the CPU to access PCI Memory (prefetch).
463 * This window will be setup with the second set of Outbound ATU registers
467 #define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
468 #define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
469 #define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
470 #define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
471 #define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
474 * Master window that allows the CPU to access PCI Memory (non-prefetch).
475 * This window will be setup with the second set of Outbound ATU registers
479 #define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
480 #define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
481 #define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
482 #define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
483 #define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
486 * Master window that allows the CPU to access PCI IO space.
487 * This window will be setup with the first set of Outbound ATU registers
491 #define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
492 #define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
493 #define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
494 #define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
495 #define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
498 /* PCIBR0 - for PCI IO*/
499 #define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */
500 #define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
501 /* PCIBR1 - prefetch and non-prefetch regions joined together */
502 #define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL
503 #define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
505 #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
507 #if CONFIG_ADSTYPE == CFG_8272ADS
508 #define CONFIG_HAS_ETH1
511 #endif /* __CONFIG_H */