2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * James F. Dougherty (jfd@cs.stanford.edu)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * Configuration settings for the MOUSSE board.
30 * See also: http://www.vooha.com/
34 /* ------------------------------------------------------------------------- */
37 * board/config.h - configuration options, board specific
44 * High Level Configuration Options
48 #define CONFIG_MPC824X 1
49 #define CONFIG_MPC8240 1
50 #define CONFIG_MOUSSE 1
51 #define CFG_ADDR_MAP_B 1
52 #define CONFIG_CONS_INDEX 1
53 #define CONFIG_BAUDRATE 9600
55 #define CONFIG_BOOTCOMMAND "tftp 100000 vmlinux.img;bootm" /* autoboot command */
57 #define CONFIG_BOOTCOMMAND "bootm ffe10000"
59 #define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
60 #define CONFIG_BOOTDELAY 3
64 * Command line configuration.
66 #include <config_cmd_default.h>
68 #define CONFIG_CMD_ASKENV
69 #define CONFIG_CMD_DATE
72 #define CONFIG_ENV_OVERWRITE 1
73 #define CONFIG_ETH_ADDR "00:10:18:10:00:06"
75 #define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */
77 #include "../board/mousse/mousse.h"
80 * Miscellaneous configurable options
82 #undef CFG_LONGHELP /* undef to save memory */
83 #define CFG_PROMPT "=>" /* Monitor Command Prompt */
84 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
85 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
86 #define CFG_MAXARGS 8 /* Max number of command args */
88 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
89 #define CFG_LOAD_ADDR 0x00100000 /* Default load address */
91 /*-----------------------------------------------------------------------
92 * Start addresses for the final memory configuration
93 * (Set up by the startup code)
94 * Please note that CFG_SDRAM_BASE _must_ start at 0
96 #define CFG_SDRAM_BASE 0x00000000
99 #define CFG_MONITOR_BASE CFG_SDRAM_BASE
101 #define CFG_MONITOR_BASE CFG_FLASH_BASE
105 #define CFG_MONITOR_LEN (4 << 20) /* lots of mem ... */
107 #define CFG_MONITOR_LEN (512 << 10) /* 512K PLCC bootrom */
109 #define CFG_MALLOC_LEN (2*(4096 << 10)) /* 2*4096kB for malloc() */
111 #define CFG_MEMTEST_START 0x00004000 /* memtest works on */
112 #define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
115 #define CFG_EUMB_ADDR 0xFC000000
117 #define CFG_ISA_MEM 0xFD000000
118 #define CFG_ISA_IO 0xFE000000
120 #define CFG_FLASH_BASE 0xFFF00000
121 #define CFG_FLASH_SIZE ((uint)(512 * 1024))
122 #define CFG_RESET_ADDRESS 0xFFF00100
123 #define FLASH_BASE0_PRELIM 0xFFF00000 /* 512K PLCC FLASH/AM29F040*/
124 #define FLASH_BASE0_SIZE 0x80000 /* 512K */
125 #define FLASH_BASE1_PRELIM 0xFFE10000 /* AMD 29LV160DB
126 1MB - 64K FLASH0 SEG =960K
129 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
132 * NS16550 Configuration
135 #define CFG_NS16550_SERIAL
137 #define CFG_NS16550_REG_SIZE 1
139 #define CFG_NS16550_CLK 18432000
141 #define CFG_NS16550_COM1 0xFFE08080
143 /*-----------------------------------------------------------------------
144 * Definitions for initial stack pointer and data area (in DPRAM)
146 #define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
147 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
148 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
149 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
150 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
153 * Low Level Configuration Settings
154 * (address mappings, register initial values, etc.)
155 * You should know what you are doing if you make changes here.
156 * For the detail description refer to the MPC8240 user's manual.
159 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
160 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2
163 #define CFG_ETH_DEV_FN 0x00
164 #define CFG_ETH_IOBASE 0x00104000
167 /* Bit-field values for MCCR1.
172 /* Bit-field values for MCCR2.
174 #define CFG_REFINT 0xf5 /* Refresh interval */
176 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
178 #define CFG_BSTOPRE 0x79
182 #else /* INCLUDE_ECC */
184 #endif /* INCLUDE_ECC */
187 /* Bit-field values for MCCR3.
189 #define CFG_REFREC 8 /* Refresh to activate interval */
190 #define CFG_RDLAT (4+USE_ECC) /* Data latancy from read command */
192 /* Bit-field values for MCCR4.
194 #define CFG_PRETOACT 3 /* Precharge to activate interval */
195 #define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
196 #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
197 #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
198 #define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
200 #define CFG_REGISTERD_TYPE_BUFFER (1-USE_ECC)
202 /* Memory bank settings.
203 * Only bits 20-29 are actually used from these vales to set the
204 * start/end addresses. The upper two bits will always be 0, and the lower
205 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
206 * address. Refer to the MPC8240 book.
208 #define CFG_RAM_SIZE 0x04000000 /* 64MB */
211 #define CFG_BANK0_START 0x00000000
212 #define CFG_BANK0_END (CFG_RAM_SIZE - 1)
213 #define CFG_BANK0_ENABLE 1
214 #define CFG_BANK1_START 0x3ff00000
215 #define CFG_BANK1_END 0x3fffffff
216 #define CFG_BANK1_ENABLE 0
217 #define CFG_BANK2_START 0x3ff00000
218 #define CFG_BANK2_END 0x3fffffff
219 #define CFG_BANK2_ENABLE 0
220 #define CFG_BANK3_START 0x3ff00000
221 #define CFG_BANK3_END 0x3fffffff
222 #define CFG_BANK3_ENABLE 0
223 #define CFG_BANK4_START 0x3ff00000
224 #define CFG_BANK4_END 0x3fffffff
225 #define CFG_BANK4_ENABLE 0
226 #define CFG_BANK5_START 0x3ff00000
227 #define CFG_BANK5_END 0x3fffffff
228 #define CFG_BANK5_ENABLE 0
229 #define CFG_BANK6_START 0x3ff00000
230 #define CFG_BANK6_END 0x3fffffff
231 #define CFG_BANK6_ENABLE 0
232 #define CFG_BANK7_START 0x3ff00000
233 #define CFG_BANK7_END 0x3fffffff
234 #define CFG_BANK7_ENABLE 0
236 #define CFG_ODCR 0x7f
239 #define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory
240 see 8240 book for details*/
241 #define PCI_MEM_SPACE1_START 0x80000000
242 #define PCI_MEM_SPACE2_START 0xfd000000
244 /* IBAT/DBAT Configuration */
245 /* Ram: 64MB, starts at address-0, r/w instruction/data */
246 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
247 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
248 #define CFG_DBAT0U CFG_IBAT0U
249 #define CFG_DBAT0L CFG_IBAT0L
251 /* MPLD/Port-X I/O Space : data and instruction read/write, cache-inhibit */
252 #define CFG_IBAT1U (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
254 #define CFG_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 | BATL_MEMCOHERENCE |\
255 BATL_WRITETHROUGH | BATL_CACHEINHIBIT)
257 #define CFG_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
259 #define CFG_DBAT1U CFG_IBAT1U
260 #define CFG_DBAT1L CFG_IBAT1L
262 /* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
263 #define CFG_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
264 #define CFG_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
265 #define CFG_DBAT2U CFG_IBAT2U
266 #define CFG_DBAT2L CFG_IBAT2L
268 /* PCI Memory region 2: PCI Devices in 0xFD space */
269 #define CFG_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
270 #define CFG_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
271 #define CFG_DBAT3U CFG_IBAT3U
272 #define CFG_DBAT3L CFG_IBAT3L
276 * For booting Linux, the board info and command line data
277 * have to be in the first 8 MB of memory, since this is
278 * the maximum mapped by the Linux kernel during initialization.
280 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
282 /*-----------------------------------------------------------------------
285 #define CFG_MAX_FLASH_BANKS 3 /* Max number of flash banks */
286 #define CFG_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
288 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
289 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
292 #define CFG_ENV_IS_IN_FLASH 1
293 #define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */
294 #define CFG_ENV_SIZE 0x4000 /* Size of the Environment Sector */
296 #define CFG_ENV_IS_IN_NVRAM 1
297 #define CFG_ENV_ADDR NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/
298 #define CFG_ENV_OFFSET CFG_ENV_ADDR
299 #define CFG_ENV_SIZE NV_U_BOOT_ENV_SIZE /* 2K */
301 /*-----------------------------------------------------------------------
302 * Cache Configuration
304 #define CFG_CACHELINE_SIZE 16
308 * Internal Definitions
312 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
313 #define BOOTFLAG_WARM 0x02 /* Software reboot */
317 #define CONFIG_ETHADDR 0:0:0:0:1:d
318 #define CONFIG_IPADDR 172.16.40.113
319 #define CONFIG_SERVERIP 172.16.40.111
321 #define CONFIG_ETHADDR 0:0:0:0:1:d
322 #define CONFIG_IPADDR 209.128.93.138
323 #define CONFIG_SERVERIP 209.128.93.133
326 /*-----------------------------------------------------------------------
328 *-----------------------------------------------------------------------
330 #define CONFIG_PCI /* include pci support */
331 #undef CONFIG_PCI_PNP
333 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
337 #endif /* __CONFIG_H */