2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
15 /***********************************************************
16 * High Level Configuration Options
18 ***********************************************************/
19 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
20 #define CONFIG_MIP405 1 /* ...on a MIP405 board */
22 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
25 /***********************************************************
26 * Note that it may also be a MIP405T board which is a subset of the
28 ***********************************************************/
29 /***********************************************************
31 * CONFIG_BOOT_PCI is only used for first boot-up and should
32 * NOT be enabled for production bootloader
33 ***********************************************************/
34 /*#define CONFIG_BOOT_PCI 1*/
35 /***********************************************************
37 ***********************************************************/
38 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
44 #define CONFIG_BOOTP_BOOTFILESIZE
45 #define CONFIG_BOOTP_BOOTPATH
46 #define CONFIG_BOOTP_GATEWAY
47 #define CONFIG_BOOTP_HOSTNAME
51 * Command line configuration.
53 #define CONFIG_CMD_CACHE
54 #define CONFIG_CMD_DATE
55 #define CONFIG_CMD_EEPROM
56 #define CONFIG_CMD_FAT
57 #define CONFIG_CMD_IDE
58 #define CONFIG_CMD_IRQ
59 #define CONFIG_CMD_JFFS2
60 #define CONFIG_CMD_MII
61 #define CONFIG_CMD_PCI
62 #define CONFIG_CMD_REGINFO
63 #define CONFIG_CMD_SAVES
64 #define CONFIG_CMD_BSP
66 #if !defined(CONFIG_MIP405T)
70 /**************************************************************
72 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
74 * The Atmel EEPROM uses 16Bit addressing.
75 ***************************************************************/
77 #define CONFIG_SYS_I2C
78 #define CONFIG_SYS_I2C_PPC4XX
79 #define CONFIG_SYS_I2C_PPC4XX_CH0
80 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
81 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
83 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
84 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
85 /* mask of address bits that overflow into the "EEPROM chip address" */
86 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
87 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
88 /* 64 byte page write mode using*/
89 /* last 6 bits of the address */
90 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
93 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
94 #define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
95 #define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
97 /***************************************************************
98 * Definitions for Serial Presence Detect EEPROM address
99 * (to get SDRAM settings)
100 ***************************************************************/
101 /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
102 #define SDRAM_EEPROM_READ_ADDRESS 0xA1
104 /**************************************************************
105 * Environment definitions
106 **************************************************************/
107 #define CONFIG_BAUDRATE 9600 /* STD Baudrate */
108 #define CONFIG_BOOTDELAY 5
109 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
110 /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
111 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
113 #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
114 #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
116 #define CONFIG_IPADDR 10.0.0.100
117 #define CONFIG_SERVERIP 10.0.0.1
118 #define CONFIG_PREBOOT
119 /***************************************************************
120 * defines if the console is stored in the environment
121 ***************************************************************/
122 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
123 /***************************************************************
124 * defines if an overwrite_console function exists
125 *************************************************************/
126 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
127 #define CONFIG_SYS_CONSOLE_INFO_QUIET
128 /***************************************************************
129 * defines if the overwrite_console should be stored in the
131 **************************************************************/
132 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
134 /**************************************************************
136 *************************************************************/
137 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
138 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
140 #define CONFIG_MISC_INIT_R
141 /***********************************************************
142 * Miscellaneous configurable options
143 **********************************************************/
144 #define CONFIG_SYS_LONGHELP /* undef to save memory */
145 #if defined(CONFIG_CMD_KGDB)
146 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
148 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
151 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
152 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
154 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
155 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
157 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
158 #define CONFIG_SYS_NS16550_SERIAL
159 #define CONFIG_SYS_NS16550_REG_SIZE 1
160 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
162 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
163 #define CONFIG_SYS_BASE_BAUD 916667
165 /* The following table includes the supported baudrates */
166 #define CONFIG_SYS_BAUDRATE_TABLE \
167 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
168 57600, 115200, 230400, 460800, 921600 }
170 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
171 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
173 /*-----------------------------------------------------------------------
175 *-----------------------------------------------------------------------
177 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
178 #define PCI_HOST_FORCE 1 /* configure as pci host */
179 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
181 #define CONFIG_PCI /* include pci support */
182 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
183 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
184 #define CONFIG_PCI_PNP /* pci plug-and-play */
185 /* resource configuration */
186 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
187 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
188 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
189 #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
190 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
191 #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
192 #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
193 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
195 /*-----------------------------------------------------------------------
196 * Start addresses for the final memory configuration
197 * (Set up by the startup code)
198 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
200 #define CONFIG_SYS_SDRAM_BASE 0x00000000
201 #define CONFIG_SYS_FLASH_BASE 0xFFF80000
202 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
203 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
204 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
207 * For booting Linux, the board info and command line data
208 * have to be in the first 8 MB of memory, since this is
209 * the maximum mapped by the Linux kernel during initialization.
211 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
212 /*-----------------------------------------------------------------------
215 #define CONFIG_SYS_UPDATE_FLASH_SIZE
216 #define CONFIG_SYS_FLASH_PROTECTION
217 #define CONFIG_SYS_FLASH_EMPTY_INFO
219 #define CONFIG_SYS_FLASH_CFI
220 #define CONFIG_FLASH_CFI_DRIVER
222 #define CONFIG_FLASH_SHOW_PROGRESS 45
224 #define CONFIG_SYS_MAX_FLASH_BANKS 1
225 #define CONFIG_SYS_MAX_FLASH_SECT 256
231 /* No command line, one static partition, whole device */
232 #undef CONFIG_CMD_MTDPARTS
233 #define CONFIG_JFFS2_DEV "nor0"
234 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
235 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
237 /* mtdparts command line support */
238 /* Note: fake mtd_id used, no linux mtd map file */
240 #define CONFIG_CMD_MTDPARTS
241 #define MTDIDS_DEFAULT "nor0=mip405-0"
242 #define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
245 /*-----------------------------------------------------------------------
246 * Logbuffer Configuration
248 #undef CONFIG_LOGBUFFER /* supported but not enabled */
249 /*-----------------------------------------------------------------------
250 * Bootcountlimit Configuration
252 #undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
254 /*-----------------------------------------------------------------------
257 #if 0 /* enable this if POST is desired (is supported but not enabled) */
258 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
259 CONFIG_SYS_POST_CPU | \
260 CONFIG_SYS_POST_RTC | \
265 * Init Memory Controller:
267 #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
268 #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
269 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
270 #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
272 #define CONFIG_BOARD_EARLY_INIT_F 1
273 #define CONFIG_BOARD_EARLY_INIT_R
275 /* Peripheral Bus Mapping */
276 #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
277 #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
278 #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
280 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
281 #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
284 /*-----------------------------------------------------------------------
285 * Definitions for initial stack pointer and data area (in On Chip SRAM)
287 #define CONFIG_SYS_TEMP_STACK_OCM 1
288 #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
289 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
290 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
291 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
292 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
293 /* reserve some memory for POST and BOOT limit info */
294 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
296 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
297 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
300 /***********************************************************************
301 * External peripheral base address
302 ***********************************************************************/
303 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
305 /***********************************************************************
307 ***********************************************************************/
308 #define CONFIG_LAST_STAGE_INIT
309 /************************************************************
311 ***********************************************************/
312 #define CONFIG_PPC4xx_EMAC
313 #define CONFIG_MII 1 /* MII PHY management */
314 #define CONFIG_PHY_ADDR 1 /* PHY address */
315 #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
316 #define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
317 /************************************************************
319 ***********************************************************/
320 #define CONFIG_RTC_MC146818
321 #undef CONFIG_WATCHDOG /* watchdog disabled */
323 /************************************************************
325 ************************************************************/
326 #if defined(CONFIG_MIP405T)
327 #define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
329 #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
332 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
334 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
335 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
336 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
337 #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
338 #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
339 #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
341 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
342 #undef CONFIG_IDE_LED /* no led for ide supported */
343 #define CONFIG_IDE_RESET /* reset for ide supported... */
344 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
345 #define CONFIG_SUPPORT_VFAT
346 /************************************************************
347 * ATAPI support (experimental)
348 ************************************************************/
349 #define CONFIG_ATAPI /* enable ATAPI Support */
351 /************************************************************
352 * DISK Partition support
353 ************************************************************/
354 #define CONFIG_DOS_PARTITION
355 #define CONFIG_MAC_PARTITION
356 #define CONFIG_ISO_PARTITION /* Experimental */
358 /************************************************************
360 ************************************************************/
361 #define CONFIG_VIDEO /*To enable video controller support */
362 #define CONFIG_VIDEO_CT69000
363 #define CONFIG_CFB_CONSOLE
364 #define CONFIG_VIDEO_LOGO
365 #define CONFIG_CONSOLE_EXTRA_INFO
366 #define CONFIG_VGA_AS_SINGLE_DEVICE
367 #define CONFIG_VIDEO_SW_CURSOR
368 #undef CONFIG_VIDEO_ONBOARD
369 /************************************************************
370 * USB support EXPERIMENTAL
371 ************************************************************/
372 #if !defined(CONFIG_MIP405T)
373 #define CONFIG_USB_UHCI
374 #define CONFIG_USB_KEYBOARD
375 #define CONFIG_USB_STORAGE
377 /* Enable needed helper functions */
378 #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
380 /************************************************************
382 ************************************************************/
383 #if defined(CONFIG_CMD_KGDB)
384 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
387 /************************************************************
388 * support BZIP2 compression
389 ************************************************************/
390 #define CONFIG_BZIP2 1
392 /************************************************************
394 ************************************************************/
396 #define VERSION_TAG "released"
397 #if !defined(CONFIG_MIP405T)
398 #define CONFIG_ISO_STRING "MEV-10072-001"
400 #define CONFIG_ISO_STRING "MEV-10082-001"
403 #if !defined(CONFIG_BOOT_PCI)
404 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
406 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
410 #endif /* __CONFIG_H */