2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
15 /***********************************************************
16 * High Level Configuration Options
18 ***********************************************************/
19 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
20 #define CONFIG_MIP405 1 /* ...on a MIP405 board */
22 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
24 /***********************************************************
25 * Note that it may also be a MIP405T board which is a subset of the
27 ***********************************************************/
28 /***********************************************************
30 * CONFIG_BOOT_PCI is only used for first boot-up and should
31 * NOT be enabled for production bootloader
32 ***********************************************************/
33 /*#define CONFIG_BOOT_PCI 1*/
34 /***********************************************************
36 ***********************************************************/
37 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
42 #define CONFIG_BOOTP_BOOTFILESIZE
43 #define CONFIG_BOOTP_BOOTPATH
44 #define CONFIG_BOOTP_GATEWAY
45 #define CONFIG_BOOTP_HOSTNAME
48 * Command line configuration.
50 #define CONFIG_CMD_CACHE
51 #define CONFIG_CMD_DATE
52 #define CONFIG_CMD_EEPROM
53 #define CONFIG_CMD_FAT
54 #define CONFIG_CMD_IDE
55 #define CONFIG_CMD_IRQ
56 #define CONFIG_CMD_JFFS2
57 #define CONFIG_CMD_MII
58 #define CONFIG_CMD_PCI
59 #define CONFIG_CMD_REGINFO
60 #define CONFIG_CMD_SAVES
61 #define CONFIG_CMD_BSP
63 #if !defined(CONFIG_MIP405T)
66 /**************************************************************
68 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
70 * The Atmel EEPROM uses 16Bit addressing.
71 ***************************************************************/
73 #define CONFIG_SYS_I2C
74 #define CONFIG_SYS_I2C_PPC4XX
75 #define CONFIG_SYS_I2C_PPC4XX_CH0
76 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
77 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
79 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
80 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
81 /* mask of address bits that overflow into the "EEPROM chip address" */
82 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
83 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
84 /* 64 byte page write mode using*/
85 /* last 6 bits of the address */
86 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
88 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
89 #define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
90 #define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
92 /***************************************************************
93 * Definitions for Serial Presence Detect EEPROM address
94 * (to get SDRAM settings)
95 ***************************************************************/
96 /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
97 #define SDRAM_EEPROM_READ_ADDRESS 0xA1
99 /**************************************************************
100 * Environment definitions
101 **************************************************************/
102 #define CONFIG_BAUDRATE 9600 /* STD Baudrate */
103 #define CONFIG_BOOTDELAY 5
104 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
105 /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
106 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
108 #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
109 #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
111 #define CONFIG_IPADDR 10.0.0.100
112 #define CONFIG_SERVERIP 10.0.0.1
113 #define CONFIG_PREBOOT
114 /***************************************************************
115 * defines if the console is stored in the environment
116 ***************************************************************/
117 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
118 /***************************************************************
119 * defines if an overwrite_console function exists
120 *************************************************************/
121 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
122 #define CONFIG_SYS_CONSOLE_INFO_QUIET
123 /***************************************************************
124 * defines if the overwrite_console should be stored in the
126 **************************************************************/
127 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
129 /**************************************************************
131 *************************************************************/
132 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
133 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
135 #define CONFIG_MISC_INIT_R
136 /***********************************************************
137 * Miscellaneous configurable options
138 **********************************************************/
139 #define CONFIG_SYS_LONGHELP /* undef to save memory */
140 #if defined(CONFIG_CMD_KGDB)
141 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
143 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
145 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
146 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
147 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
149 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
150 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
152 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
153 #define CONFIG_SYS_NS16550_SERIAL
154 #define CONFIG_SYS_NS16550_REG_SIZE 1
155 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
157 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
158 #define CONFIG_SYS_BASE_BAUD 916667
160 /* The following table includes the supported baudrates */
161 #define CONFIG_SYS_BAUDRATE_TABLE \
162 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
163 57600, 115200, 230400, 460800, 921600 }
165 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
166 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
168 /*-----------------------------------------------------------------------
170 *-----------------------------------------------------------------------
172 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
173 #define PCI_HOST_FORCE 1 /* configure as pci host */
174 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
176 #define CONFIG_PCI /* include pci support */
177 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
178 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
179 #define CONFIG_PCI_PNP /* pci plug-and-play */
180 /* resource configuration */
181 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
182 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
183 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
184 #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
185 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
186 #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
187 #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
188 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
190 /*-----------------------------------------------------------------------
191 * Start addresses for the final memory configuration
192 * (Set up by the startup code)
193 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
195 #define CONFIG_SYS_SDRAM_BASE 0x00000000
196 #define CONFIG_SYS_FLASH_BASE 0xFFF80000
197 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
198 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
199 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
202 * For booting Linux, the board info and command line data
203 * have to be in the first 8 MB of memory, since this is
204 * the maximum mapped by the Linux kernel during initialization.
206 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
207 /*-----------------------------------------------------------------------
210 #define CONFIG_SYS_UPDATE_FLASH_SIZE
211 #define CONFIG_SYS_FLASH_PROTECTION
212 #define CONFIG_SYS_FLASH_EMPTY_INFO
214 #define CONFIG_SYS_FLASH_CFI
215 #define CONFIG_FLASH_CFI_DRIVER
217 #define CONFIG_FLASH_SHOW_PROGRESS 45
219 #define CONFIG_SYS_MAX_FLASH_BANKS 1
220 #define CONFIG_SYS_MAX_FLASH_SECT 256
226 /* No command line, one static partition, whole device */
227 #undef CONFIG_CMD_MTDPARTS
228 #define CONFIG_JFFS2_DEV "nor0"
229 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
230 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
232 /* mtdparts command line support */
233 /* Note: fake mtd_id used, no linux mtd map file */
235 #define CONFIG_CMD_MTDPARTS
236 #define MTDIDS_DEFAULT "nor0=mip405-0"
237 #define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
240 /*-----------------------------------------------------------------------
241 * Logbuffer Configuration
243 #undef CONFIG_LOGBUFFER /* supported but not enabled */
244 /*-----------------------------------------------------------------------
245 * Bootcountlimit Configuration
247 #undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
249 /*-----------------------------------------------------------------------
252 #if 0 /* enable this if POST is desired (is supported but not enabled) */
253 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
254 CONFIG_SYS_POST_CPU | \
255 CONFIG_SYS_POST_RTC | \
260 * Init Memory Controller:
262 #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
263 #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
264 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
265 #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
267 #define CONFIG_BOARD_EARLY_INIT_F 1
268 #define CONFIG_BOARD_EARLY_INIT_R
270 /* Peripheral Bus Mapping */
271 #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
272 #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
273 #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
275 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
276 #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
278 /*-----------------------------------------------------------------------
279 * Definitions for initial stack pointer and data area (in On Chip SRAM)
281 #define CONFIG_SYS_TEMP_STACK_OCM 1
282 #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
283 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
284 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
285 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
286 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
287 /* reserve some memory for POST and BOOT limit info */
288 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
290 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
291 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
294 /***********************************************************************
295 * External peripheral base address
296 ***********************************************************************/
297 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
299 /***********************************************************************
301 ***********************************************************************/
302 #define CONFIG_LAST_STAGE_INIT
303 /************************************************************
305 ***********************************************************/
306 #define CONFIG_PPC4xx_EMAC
307 #define CONFIG_MII 1 /* MII PHY management */
308 #define CONFIG_PHY_ADDR 1 /* PHY address */
309 #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
310 #define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
311 /************************************************************
313 ***********************************************************/
314 #define CONFIG_RTC_MC146818
315 #undef CONFIG_WATCHDOG /* watchdog disabled */
317 /************************************************************
319 ************************************************************/
320 #if defined(CONFIG_MIP405T)
321 #define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
323 #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
326 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
328 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
329 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
330 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
331 #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
332 #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
333 #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
335 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
336 #undef CONFIG_IDE_LED /* no led for ide supported */
337 #define CONFIG_IDE_RESET /* reset for ide supported... */
338 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
339 #define CONFIG_SUPPORT_VFAT
340 /************************************************************
341 * ATAPI support (experimental)
342 ************************************************************/
343 #define CONFIG_ATAPI /* enable ATAPI Support */
345 /************************************************************
346 * DISK Partition support
347 ************************************************************/
348 #define CONFIG_DOS_PARTITION
349 #define CONFIG_MAC_PARTITION
350 #define CONFIG_ISO_PARTITION /* Experimental */
352 /************************************************************
354 ************************************************************/
355 #define CONFIG_VIDEO /*To enable video controller support */
356 #define CONFIG_VIDEO_CT69000
357 #define CONFIG_CFB_CONSOLE
358 #define CONFIG_VIDEO_LOGO
359 #define CONFIG_CONSOLE_EXTRA_INFO
360 #define CONFIG_VGA_AS_SINGLE_DEVICE
361 #define CONFIG_VIDEO_SW_CURSOR
362 #undef CONFIG_VIDEO_ONBOARD
363 /************************************************************
364 * USB support EXPERIMENTAL
365 ************************************************************/
366 #if !defined(CONFIG_MIP405T)
367 #define CONFIG_USB_UHCI
368 #define CONFIG_USB_KEYBOARD
369 #define CONFIG_USB_STORAGE
371 /* Enable needed helper functions */
372 #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
374 /************************************************************
376 ************************************************************/
377 #if defined(CONFIG_CMD_KGDB)
378 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
381 /************************************************************
382 * support BZIP2 compression
383 ************************************************************/
384 #define CONFIG_BZIP2 1
386 /************************************************************
388 ************************************************************/
390 #define VERSION_TAG "released"
391 #if !defined(CONFIG_MIP405T)
392 #define CONFIG_ISO_STRING "MEV-10072-001"
394 #define CONFIG_ISO_STRING "MEV-10082-001"
397 #if !defined(CONFIG_BOOT_PCI)
398 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
400 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
403 #endif /* __CONFIG_H */