2 * (C) Copyright 2004 Sandburst Corporation
4 * SPDX-License-Identifier: GPL-2.0+
7 /************************************************************************
8 * METROBOX.h - configuration Sandburst MetroBox
9 ***********************************************************************/
12 * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $
15 * $Log: METROBOX.h,v $
16 * Revision 1.21 2005/06/03 15:05:25 tsawyer
17 * MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB
19 * Revision 1.20 2005/04/11 20:51:11 tsawyer
22 * Revision 1.19 2005/04/06 15:13:36 tsawyer
23 * Update appropriate files to coincide with u-boot 1.1.3
25 * Revision 1.18 2005/03/10 14:16:02 tsawyer
26 * add def'n for cis8201 short etch option.
28 * Revision 1.17 2005/03/09 19:49:51 tsawyer
29 * Remove KGDB to allow use of 2nd serial port
31 * Revision 1.16 2004/12/02 19:00:23 tsawyer
32 * Add misc_init_f to turn on i2c-1 and all four fans before sdram init
34 * Revision 1.15 2004/09/15 18:04:12 tsawyer
35 * add multiple serial port support
37 * Revision 1.14 2004/09/03 15:27:51 tsawyer
38 * All metrobox boards are at 66.66 sys clock
40 * Revision 1.13 2004/08/05 20:27:46 tsawyer
41 * Remove system ace definitions, add net console support
43 * Revision 1.12 2004/07/29 20:00:13 tsawyer
46 * Revision 1.11 2004/07/21 13:44:18 tsawyer
47 * SystemACE is out, CF direct to local bus is in
49 * Revision 1.10 2004/06/29 19:08:55 tsawyer
50 * Add CONFIG_MISC_INIT_R
52 * Revision 1.9 2004/06/28 21:30:53 tsawyer
53 * Fix default BOOTARGS
55 * Revision 1.8 2004/06/17 15:51:08 tsawyer
58 * Revision 1.7 2004/06/17 15:08:49 tsawyer
61 * Revision 1.6 2004/06/15 12:33:57 tsawyer
62 * debugging checkpoint
64 * Revision 1.5 2004/06/12 19:48:28 tsawyer
65 * Debugging checkpoint
67 * Revision 1.4 2004/06/02 13:03:06 tsawyer
70 * Revision 1.3 2004/05/18 19:56:10 tsawyer
71 * Change default bootcommand to pImage.metrobox
73 * Revision 1.2 2004/05/18 14:13:44 tsawyer
74 * Add bringup values for bootargs and bootcommand.
75 * Remove definition of ipaddress and serverip addresses.
77 * Revision 1.1 2004/04/16 15:08:54 tsawyer
86 /*-----------------------------------------------------------------------
87 * High Level Configuration Options
88 *----------------------------------------------------------------------*/
89 #define CONFIG_METROBOX 1 /* Board is Metrobox */
90 #define CONFIG_440GX 1 /* Specifc GX support */
91 #define CONFIG_440 1 /* ... PPC440 family */
92 #define CONFIG_4xx 1 /* ... PPC4xx family */
93 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
94 #define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
95 #define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
97 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
99 #undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/
100 #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
102 #define CONFIG_VERY_BIG_RAM 1
103 #define CONFIG_VERSION_VARIABLE
105 #define CONFIG_IDENT_STRING " Sandburst Metrobox"
107 /*-----------------------------------------------------------------------
108 * Base addresses -- Note these are effective addresses where the
109 * actual resources get mapped (not physical addresses)
110 *----------------------------------------------------------------------*/
111 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
112 #define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
113 #define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */
114 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
115 #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
116 #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
118 #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
119 #define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
120 #define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
121 #define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
123 /*-----------------------------------------------------------------------
124 * Initial RAM & stack pointer (placed in internal SRAM)
125 *----------------------------------------------------------------------*/
126 #define CONFIG_SYS_TEMP_STACK_OCM 1
127 #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
128 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
129 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
131 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
132 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
134 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
135 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
137 /*-----------------------------------------------------------------------
139 *----------------------------------------------------------------------*/
140 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
141 #define CONFIG_SYS_NS16550
142 #define CONFIG_SYS_NS16550_SERIAL
143 #define CONFIG_SYS_NS16550_REG_SIZE 1
144 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
145 #define CONFIG_BAUDRATE 9600
147 #define CONFIG_SYS_BAUDRATE_TABLE \
148 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
150 /*-----------------------------------------------------------------------
153 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
154 * The DS1743 code assumes this condition (i.e. -- it assumes the base
155 * address for the RTC registers is:
157 * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
159 *----------------------------------------------------------------------*/
160 #define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
161 #define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
163 /*-----------------------------------------------------------------------
165 *----------------------------------------------------------------------*/
166 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
167 #define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
169 #undef CONFIG_SYS_FLASH_CHECKSUM
170 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
171 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
173 /*-----------------------------------------------------------------------
175 *----------------------------------------------------------------------*/
176 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
177 #define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
179 /*-----------------------------------------------------------------------
181 *----------------------------------------------------------------------*/
182 #define CONFIG_SYS_I2C
183 #define CONFIG_SYS_I2C_PPC4XX
184 #define CONFIG_SYS_I2C_PPC4XX_CH0
185 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
186 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
187 #define CONFIG_SYS_I2C_PPC4XX_CH1
188 #define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
189 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
190 #define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
192 /*-----------------------------------------------------------------------
194 *----------------------------------------------------------------------*/
195 #define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
196 #undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */
197 #undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
198 #define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
200 #define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */
201 #define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR)
203 #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
204 #define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000"
205 #define CONFIG_BOOTDELAY 5 /* disable autoboot */
207 #define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
208 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
210 /*-----------------------------------------------------------------------
212 *----------------------------------------------------------------------*/
213 #define CONFIG_PPC4xx_EMAC
214 #define CONFIG_MII 1 /* MII PHY management */
215 #define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
216 #define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
217 #define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
218 #define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
219 #define CONFIG_HAS_ETH0
220 #define CONFIG_HAS_ETH1
221 #define CONFIG_HAS_ETH2
222 #define CONFIG_HAS_ETH3
223 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
224 #define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
225 #define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
226 #define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
227 #define CONFIG_PHY_RESET_DELAY 1000
228 #define CONFIG_NETMASK 255.255.0.0
229 #define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
230 #define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
231 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
237 #define CONFIG_BOOTP_BOOTFILESIZE
238 #define CONFIG_BOOTP_BOOTPATH
239 #define CONFIG_BOOTP_GATEWAY
240 #define CONFIG_BOOTP_HOSTNAME
244 * Command line configuration.
246 #include <config_cmd_default.h>
248 #define CONFIG_CMD_PCI
249 #define CONFIG_CMD_IRQ
250 #define CONFIG_CMD_I2C
251 #define CONFIG_CMD_DHCP
252 #define CONFIG_CMD_DATE
253 #define CONFIG_CMD_BEDBUG
254 #define CONFIG_CMD_PING
255 #define CONFIG_CMD_DIAG
256 #define CONFIG_CMD_MII
257 #define CONFIG_CMD_NET
258 #define CONFIG_CMD_ELF
259 #define CONFIG_CMD_IDE
260 #define CONFIG_CMD_FAT
263 /* Include NetConsole support */
264 #define CONFIG_NETCONSOLE
266 /* Include auto complete with tabs */
267 #define CONFIG_AUTO_COMPLETE 1
268 #define CONFIG_AUTO_COMPLETE 1
269 #define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
271 #define CONFIG_SYS_LONGHELP /* undef to save memory */
272 #define CONFIG_SYS_PROMPT "MetroBox=> " /* Monitor Command Prompt */
274 #define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */
277 /*-----------------------------------------------------------------------
279 *----------------------------------------------------------------------*/
280 #if defined(CONFIG_CMD_KGDB)
281 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
283 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
285 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
286 /* Print Buffer Size */
287 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
288 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
290 /*-----------------------------------------------------------------------
292 *----------------------------------------------------------------------*/
293 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
294 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
296 /*-----------------------------------------------------------------------
297 * Compact Flash (in true IDE mode)
298 *----------------------------------------------------------------------*/
299 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
300 #undef CONFIG_IDE_LED /* no led for ide supported */
302 #define CONFIG_IDE_RESET /* reset for ide supported */
303 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
304 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
306 #define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000
307 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
308 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
309 #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
310 #define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
312 #define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride
313 to get to the correct offset */
314 #define CONFIG_DOS_PARTITION 1 /* Include dos partition */
316 /*-----------------------------------------------------------------------
318 *----------------------------------------------------------------------*/
320 #define CONFIG_PCI /* include pci support */
321 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
322 #define CONFIG_PCI_PNP /* do pci plug-and-play */
323 #define CONFIG_PCI_SCAN_SHOW /* show pci devices */
324 #define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE)
326 /* Board-specific PCI */
327 #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/
329 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
330 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
333 * For booting Linux, the board info and command line data
334 * have to be in the first 8 MB of memory, since this is
335 * the maximum mapped by the Linux kernel during initialization.
337 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
339 #if defined(CONFIG_CMD_KGDB)
340 #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
341 #define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
344 /*-----------------------------------------------------------------------
345 * Miscellaneous configurable options
346 *----------------------------------------------------------------------*/
347 #undef CONFIG_WATCHDOG /* watchdog disabled */
348 #define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */
349 #define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */
351 #endif /* __CONFIG_H */