2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Copyright (C) 2011 Matrix Vision GmbH
5 * Andre Schwarz <andre.schwarz@matrix-vision.de>
7 * SPDX-License-Identifier: GPL-2.0+
16 * High Level Configuration Options
19 #define CONFIG_MPC837x 1
20 #define CONFIG_MPC8377 1
22 #define CONFIG_SYS_TEXT_BASE 0xFC000000
25 #define CONFIG_PCI_INDIRECT_BRIDGE 1
27 #define CONFIG_MASK_AER_AO
28 #define CONFIG_DISPLAY_AER_FULL
30 #define CONFIG_MISC_INIT_R
35 #define CONFIG_TSEC_ENET
40 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
42 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
43 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
46 * Hardware Reset Configuration Word stored in EEPROM.
48 #define CONFIG_SYS_HRCW_LOW 0
49 #define CONFIG_SYS_HRCW_HIGH 0
51 /* Arbiter Configuration Register */
52 #define CONFIG_SYS_ACR_PIPE_DEP 3
53 #define CONFIG_SYS_ACR_RPTCNT 3
55 /* System Priority Control Regsiter */
56 #define CONFIG_SYS_SPCR_TSECEP 3
58 /* System Clock Configuration Register */
59 #define CONFIG_SYS_SCCR_TSEC1CM 3
60 #define CONFIG_SYS_SCCR_TSEC2CM 0
61 #define CONFIG_SYS_SCCR_SDHCCM 3
62 #define CONFIG_SYS_SCCR_ENCCM 3 /* also clock for I2C-1 */
63 #define CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_ENCCM /* must match */
64 #define CONFIG_SYS_SCCR_PCIEXP1CM 3
65 #define CONFIG_SYS_SCCR_PCIEXP2CM 3
66 #define CONFIG_SYS_SCCR_PCICM 1
67 #define CONFIG_SYS_SCCR_SATACM 0xFF
72 #define CONFIG_SYS_SICRH 0x087c0000
73 #define CONFIG_SYS_SICRL 0x40000000
76 * Output Buffer Impedance
78 #define CONFIG_SYS_OBIR 0x30000000
83 #define CONFIG_SYS_IMMR 0xE0000000
88 #define CONFIG_SYS_DDR_BASE 0x00000000
89 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
90 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
91 #define CONFIG_SYS_83XX_DDR_USES_CS0
93 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN | DDRCDR_PZ_HIZ |\
94 DDRCDR_NZ_HIZ | DDRCDR_ODT |\
97 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
99 #define CONFIG_SYS_DDR_MODE_WEAK
100 #define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2
101 #define CONFIG_SYS_DDR_CPO 0x1f
103 /* SPD table located at offset 0x20 in extended adressing ROM
104 * used for HRCW fetch after power-on reset
106 #define CONFIG_SPD_EEPROM
107 #define SPD_EEPROM_ADDRESS 0x50
108 #define SPD_EEPROM_OFFSET 0x20
109 #define SPD_EEPROM_ADDR_LEN 2
112 * The reserved memory
114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
115 #define CONFIG_SYS_MONITOR_LEN (512*1024)
116 #define CONFIG_SYS_MALLOC_LEN (512*1024)
119 * Initial RAM Base Address Setup
121 #define CONFIG_SYS_INIT_RAM_LOCK 1
122 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
123 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
124 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
125 GENERATED_GBL_DATA_SIZE)
128 * Local Bus Configuration & Clock Setup
130 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
131 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
132 #define CONFIG_SYS_LBC_LBCR 0x00000000
133 #define CONFIG_FSL_ELBC 1
136 * FLASH on the Local Bus
138 #define CONFIG_SYS_FLASH_CFI
139 #define CONFIG_FLASH_CFI_DRIVER
140 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
142 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
143 #define CONFIG_SYS_FLASH_SIZE 64
145 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
146 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
148 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
150 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
151 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
152 OR_GPCM_XACS | OR_GPCM_SCY_15 |\
153 OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
156 #define CONFIG_SYS_MAX_FLASH_BANKS 1
157 #define CONFIG_SYS_MAX_FLASH_SECT 512
159 #undef CONFIG_SYS_FLASH_CHECKSUM
160 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (ms) */
161 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
164 * NAND Flash on the Local Bus
166 #define CONFIG_MTD_NAND_VERIFY_WRITE 1
167 #define CONFIG_SYS_MAX_NAND_DEVICE 1
168 #define CONFIG_NAND_FSL_ELBC 1
170 #define CONFIG_SYS_NAND_BASE 0xE0600000
171 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
172 BR_PS_8 | BR_MS_FCM | BR_V)
173 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
174 OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
175 OR_FCM_TRLX | OR_FCM_EHTR)
177 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
178 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
183 #define CONFIG_CONS_INDEX 1
184 #define CONFIG_SYS_NS16550
185 #define CONFIG_SYS_NS16550_SERIAL
186 #define CONFIG_SYS_NS16550_REG_SIZE 1
187 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
189 #define CONFIG_SYS_BAUDRATE_TABLE \
190 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
192 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
193 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
195 #define CONFIG_CONSOLE ttyS0
196 #define CONFIG_BAUDRATE 115200
199 #define CONFIG_FSL_SERDES
200 #define CONFIG_FSL_SERDES1 0xe3000
201 #define CONFIG_FSL_SERDES2 0xe3100
203 /* Use the HUSH parser */
204 #define CONFIG_SYS_HUSH_PARSER
206 /* Pass open firmware flat tree */
207 #define CONFIG_OF_LIBFDT 1
208 #define CONFIG_OF_BOARD_SETUP 1
209 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
212 #define CONFIG_SYS_I2C
213 #define CONFIG_SYS_I2C_FSL
214 #define CONFIG_SYS_FSL_I2C_SPEED 400000
215 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
216 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
217 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
218 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
219 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
223 * Addresses are mapped 1-1.
225 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
226 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
227 #define CONFIG_SYS_PCI_MEM_SIZE (256 << 20)
228 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
229 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
230 #define CONFIG_SYS_PCI_MMIO_SIZE (256 << 20)
231 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
232 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
233 #define CONFIG_SYS_PCI_IO_SIZE (1 << 20)
236 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
237 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
238 #define CONFIG_SYS_PCIE1_CFG_SIZE (128 << 20)
239 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
240 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
241 #define CONFIG_SYS_PCIE1_MEM_SIZE (256 << 20)
242 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
243 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
244 #define CONFIG_SYS_PCIE1_IO_SIZE (8 << 20)
246 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
247 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
248 #define CONFIG_SYS_PCIE2_CFG_SIZE (128 << 20)
249 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
250 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
251 #define CONFIG_SYS_PCIE2_MEM_SIZE (256 << 20)
252 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
253 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
254 #define CONFIG_SYS_PCIE2_IO_SIZE (8 << 20)
257 #define CONFIG_PCI_PNP
258 #define CONFIG_PCI_SCAN_SHOW
259 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
264 #define CONFIG_GMII /* MII PHY management */
265 #define CONFIG_SYS_VSC8601_SKEWFIX
266 #define CONFIG_SYS_VSC8601_SKEW_TX 3
267 #define CONFIG_SYS_VSC8601_SKEW_RX 3
270 #define CONFIG_HAS_ETH0
271 #define CONFIG_TSEC1_NAME "TSEC0"
272 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
273 #define TSEC1_PHY_ADDR 0x10
274 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
275 #define TSEC1_PHYIDX 0
277 #define CONFIG_ETHPRIME "TSEC0"
278 #define CONFIG_HAS_ETH0
283 #define CONFIG_LIBATA
284 #define CONFIG_FSL_SATA
286 #define CONFIG_SYS_SATA_MAX_DEVICE 2
288 #define CONFIG_SYS_SATA1_OFFSET 0x18000
289 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
290 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
292 #define CONFIG_SYS_SATA2_OFFSET 0x19000
293 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
294 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
297 #define CONFIG_CMD_SATA
298 #define CONFIG_DOS_PARTITION
299 #define CONFIG_CMD_EXT2
304 #define CONFIG_BOOTP_BOOTFILESIZE
305 #define CONFIG_BOOTP_BOOTPATH
306 #define CONFIG_BOOTP_GATEWAY
307 #define CONFIG_BOOTP_HOSTNAME
308 #define CONFIG_BOOTP_VENDOREX
309 #define CONFIG_BOOTP_SUBNETMASK
310 #define CONFIG_BOOTP_DNS
311 #define CONFIG_BOOTP_DNS2
312 #define CONFIG_BOOTP_NTPSERVER
313 #define CONFIG_BOOTP_RANDOM_DELAY
314 #define CONFIG_BOOTP_SEND_HOSTNAME
315 #define CONFIG_LIB_RAND
318 * Command line configuration.
320 #include <config_cmd_default.h>
322 #define CONFIG_CMD_ASKENV
323 #define CONFIG_CMD_NAND
324 #define CONFIG_CMD_PING
325 #define CONFIG_CMD_EEPROM
326 #define CONFIG_CMD_I2C
327 #define CONFIG_CMD_MII
328 #define CONFIG_CMD_PCI
329 #define CONFIG_CMD_USB
330 #define CONFIG_CMD_SPI
331 #define CONFIG_CMD_DHCP
332 #define CONFIG_CMD_UBI
333 #define CONFIG_CMD_UBIFS
334 #define CONFIG_CMD_MTDPARTS
335 #define CONFIG_CMD_SATA
337 #define CONFIG_CMD_EXT2
338 #define CONFIG_CMD_FAT
339 #define CONFIG_CMD_JFFS2
341 #define CONFIG_RBTREE
344 #define CONFIG_MTD_DEVICE
345 #define CONFIG_MTD_PARTITIONS
347 #define CONFIG_FLASH_CFI_MTD
348 #define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND"
349 #define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)"
352 #define CONFIG_FIT_VERBOSE 1
354 #define CONFIG_CMDLINE_EDITING 1
355 #define CONFIG_AUTO_COMPLETE
358 * Miscellaneous configurable options
360 #define CONFIG_SYS_LONGHELP
361 #define CONFIG_SYS_LOAD_ADDR 0x2000000
362 #define CONFIG_LOADADDR 0x4000000
363 #define CONFIG_SYS_CBSIZE 256
365 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
366 #define CONFIG_SYS_MAXARGS 16
367 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
369 #define CONFIG_LOADS_ECHO 1
370 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1
372 #define CONFIG_SYS_MEMTEST_START (60<<20)
373 #define CONFIG_SYS_MEMTEST_END (70<<20)
376 * For booting Linux, the board info and command line data
377 * have to be in the first 256 MB of memory, since this is
378 * the maximum mapped by the Linux kernel during initialization.
380 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
385 #define CONFIG_SYS_HID0_INIT 0x000000000
386 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
387 HID0_ENABLE_INSTRUCTION_CACHE)
388 #define CONFIG_SYS_HID2 HID2_HBE
393 #define CONFIG_HIGH_BATS 1
395 /* DDR: cache cacheable */
396 #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE
398 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_RW |\
400 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
402 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
403 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
406 #define CONFIG_SYS_IBAT1L (0)
407 #define CONFIG_SYS_IBAT1U (0)
408 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
409 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
411 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
412 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW |\
413 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
414 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
416 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
417 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
420 #define CONFIG_SYS_IBAT3L (0)
421 #define CONFIG_SYS_IBAT3U (0)
422 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
423 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
425 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
426 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\
428 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
430 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
431 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
432 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
434 /* Stack in dcache: cacheable, no memory coherence */
435 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
436 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
438 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
439 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
441 /* PCI MEM space: cacheable */
442 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\
444 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
446 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
447 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
449 /* PCI MMIO space: cache-inhibit and guarded */
450 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \
451 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
452 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
454 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
455 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
458 * I2C EEPROM settings
460 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
461 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
462 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
463 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
464 #define CONFIG_SYS_EEPROM_SIZE 0x4000
467 * Environment Configuration
469 #define CONFIG_SYS_FLASH_PROTECTION
470 #define CONFIG_ENV_OVERWRITE
471 #define CONFIG_ENV_IS_IN_FLASH 1
472 #define CONFIG_ENV_ADDR 0xFFD00000
473 #define CONFIG_ENV_SECT_SIZE 0x20000
474 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
480 #define CONFIG_VIDEO_SM501_PCI
481 #define VIDEO_FB_LITTLE_ENDIAN
482 #define CONFIG_CMD_BMP
483 #define CONFIG_VIDEO_SM501
484 #define CONFIG_VIDEO_SM501_32BPP
485 #define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
486 #define CONFIG_CFB_CONSOLE
487 #define CONFIG_VIDEO_LOGO
488 #define CONFIG_VIDEO_BMP_LOGO
489 #define CONFIG_VGA_AS_SINGLE_DEVICE
490 #define CONFIG_SPLASH_SCREEN
491 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
492 #define CONFIG_VIDEO_BMP_GZIP
493 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
498 #define CONFIG_MPC8XXX_SPI
503 #define CONFIG_SYS_USB_HOST
504 #define CONFIG_USB_EHCI
505 #define CONFIG_USB_EHCI_FSL
506 #define CONFIG_HAS_FSL_DR_USB
507 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
509 #define CONFIG_USB_STORAGE
510 #define CONFIG_USB_KEYBOARD
514 #define CONFIG_BOOTDELAY 5
515 #define CONFIG_AUTOBOOT_KEYED
516 #define CONFIG_AUTOBOOT_STOP_STR "s"
517 #define CONFIG_ZERO_BOOTDELAY_CHECK
518 #define CONFIG_RESET_TO_RETRY 1000
520 #define MV_CI "MergerBox"
521 #define MV_VCI "MergerBox"
522 #define MV_FPGA_DATA 0xfc100000
523 #define MV_FPGA_SIZE 0x00200000
525 #define CONFIG_SHOW_BOOT_PROGRESS 1
527 #define MV_KERNEL_ADDR_RAM 0x02800000
528 #define MV_DTB_ADDR_RAM 0x00600000
529 #define MV_INITRD_ADDR_RAM 0x01000000
530 #define MV_FITADDR 0xfc300000
531 #define MV_SPLAH_ADDR 0xffe00000
533 #define CONFIG_BOOTCOMMAND "run i2c_init;if test ${boot_sqfs} -eq 1;"\
534 "then; run fitboot;else;run ubiboot;fi;"
535 #define CONFIG_BOOTARGS "console=ttyS0,115200n8"
537 #define CONFIG_EXTRA_ENV_SETTINGS \
543 "usb_dr_mode=host\0"\
544 "bootfile=MergerBox.fit\0"\
545 "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\
547 "fpgadata=" __stringify(MV_FPGA_DATA) "\0"\
548 "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\
549 "mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\
550 "mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\
551 "mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\
552 "uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\
553 "fitaddr=" __stringify(MV_FITADDR) "\0"\
554 "mv_version=" U_BOOT_VERSION "\0"\
555 "mtdids=" MTDIDS_DEFAULT "\0"\
556 "mtdparts=" MTDPARTS_DEFAULT "\0"\
557 "dhcp_client_id=" MV_CI "\0"\
558 "dhcp_vendor-class-identifier=" MV_VCI "\0"\
559 "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
560 "protect off all;erase $uboota +0xC0000;"\
561 "cp.b $loadaddr $uboota $filesize\0"\
562 "upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\
563 "cp.b $loadaddr $fpgadata $filesize\0"\
564 "upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\
565 "cp.b $loadaddr $fitaddr $filesize\0"\
566 "addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\
567 "rootfstype=squashfs\0"\
568 "addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\
569 "rootfstype=ubifs\0"\
570 "addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\
571 "rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\
572 "netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\
573 "netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\
574 "ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\
575 "doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\
576 "fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\
577 "imxtract $fitaddr ramdisk $mv_initrd_ram;"\
578 "imxtract $fitaddr fdt $mv_dtb_ram\0"\
579 "fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\
580 "fitboot=run fitprep fdtprep addsqshrfs doboot\0"\
581 "i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\
582 "i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\
583 "i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\
584 "i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\
585 "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
586 "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
587 "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
588 "splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\
594 #define CONFIG_FPGA_COUNT 1
596 #define CONFIG_FPGA_ALTERA
597 #define CONFIG_FPGA_CYCLON2