3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
6 * Configuation settings for the MBX8xx board.
8 * -----------------------------------------------------------------
9 * SPDX-License-Identifier: GPL-2.0+
13 * Added PCMCIA defines mostly taken from other U-Boot boards that
14 * have PCMCIA already working. If you find any bugs, incorrect assumptions
15 * feel free to fix them yourself and submit a patch.
16 * Rod Boyce <rod_boyce@stratexnet.com.
19 * board/config.h - configuration options, board specific
26 * High Level Configuration Options
30 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */
31 #define CONFIG_MBX 1 /* ...on an MBX module */
33 #define CONFIG_SYS_TEXT_BASE 0xfe000000
35 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
36 #undef CONFIG_8xx_CONS_SMC2
37 #undef CONFIG_8xx_CONS_NONE
38 #define CONFIG_BAUDRATE 9600
39 /* Define this to use the PCI bus */
42 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
43 #define CONFIG_8xx_GCLK_FREQ (50000000UL)
45 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49 #define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */
51 #define CONFIG_BOOTARGS "root=/dev/nfs rw " \
52 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
53 "nfsaddrs=10.0.0.99:10.0.0.2"
55 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
56 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
58 #undef CONFIG_WATCHDOG /* watchdog disabled */
64 #define CONFIG_BOOTP_BOOTFILESIZE
65 #define CONFIG_BOOTP_BOOTPATH
66 #define CONFIG_BOOTP_GATEWAY
67 #define CONFIG_BOOTP_HOSTNAME
71 * Command line configuration.
73 #define CONFIG_CMD_NET
74 #define CONFIG_CMD_SDRAM
75 #define CONFIG_CMD_PCMCIA
76 #define CONFIG_CMD_IDE
79 #define CONFIG_DOS_PARTITION
82 * Miscellaneous configurable options
84 #define CONFIG_SYS_LONGHELP /* undef to save memory */
85 #undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */
86 #if defined(CONFIG_CMD_KGDB)
87 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
89 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
91 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
92 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
93 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
95 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
96 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
98 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
100 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
103 * Low Level Configuration Settings
104 * (address mappings, register initial values, etc.)
105 * You should know what you are doing if you make changes here.
108 /*-----------------------------------------------------------------------
109 * Physical memory map as defined by the MBX PGM
111 #define CONFIG_SYS_IMMR 0xFA200000 /* Internal Memory Mapped Register*/
112 #define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM */
113 #define CONFIG_SYS_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */
114 #define CONFIG_SYS_CSR_BASE 0xFA100000 /* Control/Status Registers */
115 #define CONFIG_SYS_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */
116 #define CONFIG_SYS_PCIMEM_OR 0xA0000108
117 #define CONFIG_SYS_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */
118 #define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108
120 /*-----------------------------------------------------------------------
121 * Definitions for initial stack pointer and data area (in DPRAM)
123 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
124 #define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */
125 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
126 #define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
127 #define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
128 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
130 /*-----------------------------------------------------------------------
131 * Offset in DPMEM where we keep the VPD data
133 #define CONFIG_SYS_DPRAMVPD (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000)
135 /*-----------------------------------------------------------------------
136 * Start addresses for the final memory configuration
137 * (Set up by the startup code)
138 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
140 #define CONFIG_SYS_SDRAM_BASE 0x00000000
141 #define CONFIG_SYS_FLASH_BASE 0xfe000000
143 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
145 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
147 #undef CONFIG_SYS_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */
148 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
149 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
152 * For booting Linux, the board info and command line data
153 * have to be in the first 8 MB of memory, since this is
154 * the maximum mapped by the Linux kernel during initialization.
156 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
158 /*-----------------------------------------------------------------------
161 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
162 #define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
164 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
165 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
167 /*-----------------------------------------------------------------------
168 * NVRAM Configuration
170 * Note: the MBX is special because there is already a firmware on this
171 * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
172 * access the NVRAM at the offset 0x1000.
174 #define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */
175 #define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000)
176 #define CONFIG_ENV_SIZE 0x1000
178 /*-----------------------------------------------------------------------
179 * Cache Configuration
181 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
182 #if defined(CONFIG_CMD_KGDB)
183 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
186 /*-----------------------------------------------------------------------
187 * SYPCR - System Protection Control 11-9
188 * SYPCR can only be written once after reset!
189 *-----------------------------------------------------------------------
190 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
192 #if defined(CONFIG_WATCHDOG)
193 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
194 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
196 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
199 /*-----------------------------------------------------------------------
200 * SIUMCR - SIU Module Configuration 11-6
201 *-----------------------------------------------------------------------
202 * PCMCIA config., multi-function pin tri-state
204 /* #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */
205 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC )
207 /*-----------------------------------------------------------------------
208 * TBSCR - Time Base Status and Control 11-26
209 *-----------------------------------------------------------------------
210 * Clear Reference Interrupt Status, Timebase freezing enabled
212 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
214 /*-----------------------------------------------------------------------
215 * PISCR - Periodic Interrupt Status and Control 11-31
216 *-----------------------------------------------------------------------
217 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
219 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
221 /*-----------------------------------------------------------------------
222 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
223 *-----------------------------------------------------------------------
224 * Reset PLL lock status sticky bit, timer expired status bit and timer
225 * interrupt status bit - leave PLL multiplication factor unchanged !
227 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
229 /*-----------------------------------------------------------------------
230 * SCCR - System Clock and reset Control Register 15-27
231 *-----------------------------------------------------------------------
232 * Set clock output, timebase and RTC source and divider,
233 * power management and some other internal clocks
235 #define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL)
236 #define CONFIG_SYS_SCCR SCCR_TBS
238 /*-----------------------------------------------------------------------
240 *-----------------------------------------------------------------------
243 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
244 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
245 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
246 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
247 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
248 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
249 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
250 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
252 #define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6
254 #define CONFIG_PCMCIA_SLOT_A 1
257 /*-----------------------------------------------------------------------
258 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
259 *-----------------------------------------------------------------------
262 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
263 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
265 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
266 #undef CONFIG_IDE_LED /* LED for ide not supported */
267 #undef CONFIG_IDE_RESET /* reset for ide not supported */
269 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
270 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
272 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
274 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
276 /* Offset for data I/O */
277 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
279 /* Offset for normal register accesses */
280 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
282 /* Offset for alternate registers */
283 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
285 /*-----------------------------------------------------------------------
287 *-----------------------------------------------------------------------
290 #define CONFIG_SYS_DER 0
292 #endif /* __CONFIG_H */