include/configs/M54455EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF54455 EVB board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54455EVB_H
  15 #define _M54455EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M54455EVB        /* M54455EVB board */
  22
  23 #define CONFIG_DISPLAY_BOARDINFO
  24
  25 #define CONFIG_MCFUART
  26 #define CONFIG_SYS_UART_PORT            (0)
  27 #define CONFIG_BAUDRATE         115200
  28
  29 #undef CONFIG_WATCHDOG
  30
  31 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  32
  33 /*
  34  * BOOTP options
  35  */
  36 #define CONFIG_BOOTP_BOOTFILESIZE
  37 #define CONFIG_BOOTP_BOOTPATH
  38 #define CONFIG_BOOTP_GATEWAY
  39 #define CONFIG_BOOTP_HOSTNAME
  40
  41 /* Command line configuration */
  42 #define CONFIG_CMD_DATE
  43 #define CONFIG_CMD_IDE
  44 #define CONFIG_CMD_JFFS2
  45 #undef CONFIG_CMD_PCI
  46 #define CONFIG_CMD_REGINFO
  47
  48 /* Network configuration */
  49 #define CONFIG_MCFFEC
  50 #ifdef CONFIG_MCFFEC
  51 #       define CONFIG_MII               1
  52 #       define CONFIG_MII_INIT          1
  53 #       define CONFIG_SYS_DISCOVER_PHY
  54 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  55 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  56
  57 #       define CONFIG_SYS_FEC0_PINMUX   0
  58 #       define CONFIG_SYS_FEC1_PINMUX   0
  59 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  60 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  61 #       define MCFFEC_TOUT_LOOP 50000
  62 #       define CONFIG_HAS_ETH1
  63
  64 #       define CONFIG_BOOTDELAY 1       /* autoboot after 5 seconds */
  65 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
  66 #       define CONFIG_ETHPRIME          "FEC0"
  67 #       define CONFIG_IPADDR            192.162.1.2
  68 #       define CONFIG_NETMASK           255.255.255.0
  69 #       define CONFIG_SERVERIP          192.162.1.1
  70 #       define CONFIG_GATEWAYIP         192.162.1.1
  71
  72 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  73 #       ifndef CONFIG_SYS_DISCOVER_PHY
  74 #               define FECDUPLEX        FULL
  75 #               define FECSPEED         _100BASET
  76 #       else
  77 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  78 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  79 #               endif
  80 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  81 #endif
  82
  83 #define CONFIG_HOSTNAME         M54455EVB
  84 #ifdef CONFIG_SYS_STMICRO_BOOT
  85 /* ST Micro serial flash */
  86 #define CONFIG_SYS_LOAD_ADDR2           0x40010013
  87 #define CONFIG_EXTRA_ENV_SETTINGS               \
  88         "netdev=eth0\0"                         \
  89         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  90         "loadaddr=0x40010000\0"                 \
  91         "sbfhdr=sbfhdr.bin\0"                   \
  92         "uboot=u-boot.bin\0"                    \
  93         "load=tftp ${loadaddr} ${sbfhdr};"      \
  94         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
  95         "upd=run load; run prog\0"              \
  96         "prog=sf probe 0:1 1000000 3;"          \
  97         "sf erase 0 30000;"                     \
  98         "sf write ${loadaddr} 0 0x30000;"       \
  99         "save\0"                                \
 100         ""
 101 #else
 102 /* Atmel and Intel */
 103 #ifdef CONFIG_SYS_ATMEL_BOOT
 104 #       define CONFIG_SYS_UBOOT_END     0x0403FFFF
 105 #elif defined(CONFIG_SYS_INTEL_BOOT)
 106 #       define CONFIG_SYS_UBOOT_END     0x3FFFF
 107 #endif
 108 #define CONFIG_EXTRA_ENV_SETTINGS               \
 109         "netdev=eth0\0"                         \
 110         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 111         "loadaddr=0x40010000\0"                 \
 112         "uboot=u-boot.bin\0"                    \
 113         "load=tftp ${loadaddr} ${uboot}\0"      \
 114         "upd=run load; run prog\0"              \
 115         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
 116         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
 117         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
 118         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
 119         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
 120         " ${filesize}; save\0"                  \
 121         ""
 122 #endif
 123
 124 /* ATA configuration */
 125 #define CONFIG_ISO_PARTITION
 126 #define CONFIG_DOS_PARTITION
 127 #define CONFIG_IDE_RESET        1
 128 #define CONFIG_IDE_PREINIT      1
 129 #define CONFIG_ATAPI
 130 #undef CONFIG_LBA48
 131
 132 #define CONFIG_SYS_IDE_MAXBUS           1
 133 #define CONFIG_SYS_IDE_MAXDEVICE        2
 134
 135 #define CONFIG_SYS_ATA_BASE_ADDR        0x90000000
 136 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
 137
 138 #define CONFIG_SYS_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O                            */
 139 #define CONFIG_SYS_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
 140 #define CONFIG_SYS_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers           */
 141 #define CONFIG_SYS_ATA_STRIDE           4       /* Interval between registers                 */
 142
 143 /* Realtime clock */
 144 #define CONFIG_MCFRTC
 145 #undef RTC_DEBUG
 146 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 147
 148 /* Timer */
 149 #define CONFIG_MCFTMR
 150 #undef CONFIG_MCFPIT
 151
 152 /* I2c */
 153 #define CONFIG_SYS_I2C
 154 #define CONFIG_SYS_I2C_FSL
 155 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 156 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 157 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 158 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 159
 160 /* DSPI and Serial Flash */
 161 #define CONFIG_CF_SPI
 162 #define CONFIG_CF_DSPI
 163 #define CONFIG_HARD_SPI
 164 #define CONFIG_SYS_SBFHDR_SIZE          0x13
 165 #ifdef CONFIG_CMD_SPI
 166
 167 #       define CONFIG_SYS_DSPI_CTAR0            (DSPI_CTAR_TRSZ(7) | \
 168                                          DSPI_CTAR_PCSSCK_1CLK | \
 169                                          DSPI_CTAR_PASC(0) | \
 170                                          DSPI_CTAR_PDT(0) | \
 171                                          DSPI_CTAR_CSSCK(0) | \
 172                                          DSPI_CTAR_ASC(0) | \
 173                                          DSPI_CTAR_DT(1))
 174 #endif
 175
 176 /* PCI */
 177 #ifdef CONFIG_CMD_PCI
 178 #define CONFIG_PCI              1
 179 #define CONFIG_PCI_PNP          1
 180 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 181
 182 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  4
 183
 184 #define CONFIG_SYS_PCI_MEM_BUS          0xA0000000
 185 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
 186 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 187
 188 #define CONFIG_SYS_PCI_IO_BUS           0xB1000000
 189 #define CONFIG_SYS_PCI_IO_PHYS          CONFIG_SYS_PCI_IO_BUS
 190 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000
 191
 192 #define CONFIG_SYS_PCI_CFG_BUS          0xB0000000
 193 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
 194 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
 195 #endif
 196
 197 /* FPGA - Spartan 2 */
 198 /* experiment
 199 #define CONFIG_FPGA
 200 #define CONFIG_FPGA_COUNT       1
 201 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 202 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 203 */
 204
 205 /* Input, PCI, Flexbus, and VCO */
 206 #define CONFIG_EXTRA_CLOCK
 207
 208 #define CONFIG_PRAM             2048    /* 2048 KB */
 209
 210 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 211
 212 #if defined(CONFIG_CMD_KGDB)
 213 #define CONFIG_SYS_CBSIZE                       1024    /* Console I/O Buffer Size */
 214 #else
 215 #define CONFIG_SYS_CBSIZE                       256     /* Console I/O Buffer Size */
 216 #endif
 217 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 218 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 219 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 220
 221 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 222
 223 #define CONFIG_SYS_MBAR         0xFC000000
 224
 225 /*
 226  * Low Level Configuration Settings
 227  * (address mappings, register initial values, etc.)
 228  * You should know what you are doing if you make changes here.
 229  */
 230
 231 /*-----------------------------------------------------------------------
 232  * Definitions for initial stack pointer and data area (in DPRAM)
 233  */
 234 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 235 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
 236 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 237 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 238 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 239 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 240
 241 /*-----------------------------------------------------------------------
 242  * Start addresses for the final memory configuration
 243  * (Set up by the startup code)
 244  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 245  */
 246 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 247 #define CONFIG_SYS_SDRAM_BASE1          0x48000000
 248 #define CONFIG_SYS_SDRAM_SIZE           256     /* SDRAM size in MB */
 249 #define CONFIG_SYS_SDRAM_CFG1           0x65311610
 250 #define CONFIG_SYS_SDRAM_CFG2           0x59670000
 251 #define CONFIG_SYS_SDRAM_CTRL           0xEA0B2000
 252 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 253 #define CONFIG_SYS_SDRAM_MODE           0x00010033
 254 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0xAA
 255
 256 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 257 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 258
 259 #ifdef CONFIG_CF_SBF
 260 #       define CONFIG_SERIAL_BOOT
 261 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 262 #else
 263 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 264 #endif
 265 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 266 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 267
 268 /* Reserve 256 kB for malloc() */
 269 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 270
 271 /*
 272  * For booting Linux, the board info and command line data
 273  * have to be in the first 8 MB of memory, since this is
 274  * the maximum mapped by the Linux kernel during initialization ??
 275  */
 276 /* Initial Memory map for Linux */
 277 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 278
 279 /*
 280  * Configuration for environment
 281  * Environment is not embedded in u-boot. First time runing may have env
 282  * crc error warning if there is no correct environment on the flash.
 283  */
 284 #ifdef CONFIG_CF_SBF
 285 #       define CONFIG_ENV_IS_IN_SPI_FLASH
 286 #       define CONFIG_ENV_SPI_CS                1
 287 #else
 288 #       define CONFIG_ENV_IS_IN_FLASH   1
 289 #endif
 290 #undef CONFIG_ENV_OVERWRITE
 291
 292 /*-----------------------------------------------------------------------
 293  * FLASH organization
 294  */
 295 #ifdef CONFIG_SYS_STMICRO_BOOT
 296 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 297 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS1_BASE
 298 #       define CONFIG_ENV_OFFSET                0x30000
 299 #       define CONFIG_ENV_SIZE          0x2000
 300 #       define CONFIG_ENV_SECT_SIZE     0x10000
 301 #endif
 302 #ifdef CONFIG_SYS_ATMEL_BOOT
 303 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 304 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 305 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 306 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 307 #       define CONFIG_ENV_SIZE          0x2000
 308 #       define CONFIG_ENV_SECT_SIZE     0x10000
 309 #endif
 310 #ifdef CONFIG_SYS_INTEL_BOOT
 311 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 312 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 313 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 314 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 315 #       define CONFIG_ENV_SIZE          0x2000
 316 #       define CONFIG_ENV_SECT_SIZE     0x20000
 317 #endif
 318
 319 #define CONFIG_SYS_FLASH_CFI
 320 #ifdef CONFIG_SYS_FLASH_CFI
 321
 322 #       define CONFIG_FLASH_CFI_DRIVER  1
 323 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 324 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 325 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_8BIT
 326 #       define CONFIG_SYS_MAX_FLASH_BANKS       2       /* max number of memory banks */
 327 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 328 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 329 #       define CONFIG_SYS_FLASH_CHECKSUM
 330 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 331 #       define CONFIG_FLASH_CFI_LEGACY
 332
 333 #ifdef CONFIG_FLASH_CFI_LEGACY
 334 #       define CONFIG_SYS_ATMEL_REGION          4
 335 #       define CONFIG_SYS_ATMEL_TOTALSECT       11
 336 #       define CONFIG_SYS_ATMEL_SECT            {1, 2, 1, 7}
 337 #       define CONFIG_SYS_ATMEL_SECTSZ          {0x4000, 0x2000, 0x8000, 0x10000}
 338 #endif
 339 #endif
 340
 341 /*
 342  * This is setting for JFFS2 support in u-boot.
 343  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 344  */
 345 #ifdef CONFIG_CMD_JFFS2
 346 #ifdef CF_STMICRO_BOOT
 347 #       define CONFIG_JFFS2_DEV         "nor1"
 348 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 349 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
 350 #endif
 351 #ifdef CONFIG_SYS_ATMEL_BOOT
 352 #       define CONFIG_JFFS2_DEV         "nor1"
 353 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 354 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
 355 #endif
 356 #ifdef CONFIG_SYS_INTEL_BOOT
 357 #       define CONFIG_JFFS2_DEV         "nor0"
 358 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x500000)
 359 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 360 #endif
 361 #endif
 362
 363 /*-----------------------------------------------------------------------
 364  * Cache Configuration
 365  */
 366 #define CONFIG_SYS_CACHELINE_SIZE               16
 367
 368 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 369                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 370 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 371                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 372 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 373 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 374 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 375                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 376                                          CF_ACR_EN | CF_ACR_SM_ALL)
 377 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 378                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 379 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 380                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 381                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 382
 383 /*-----------------------------------------------------------------------
 384  * Memory bank definitions
 385  */
 386 /*
 387  * CS0 - NOR Flash 1, 2, 4, or 8MB
 388  * CS1 - CompactFlash and registers
 389  * CS2 - CPLD
 390  * CS3 - FPGA
 391  * CS4 - Available
 392  * CS5 - Available
 393  */
 394
 395 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
 396  /* Atmel Flash */
 397 #define CONFIG_SYS_CS0_BASE             0x04000000
 398 #define CONFIG_SYS_CS0_MASK             0x00070001
 399 #define CONFIG_SYS_CS0_CTRL             0x00001140
 400 /* Intel Flash */
 401 #define CONFIG_SYS_CS1_BASE             0x00000000
 402 #define CONFIG_SYS_CS1_MASK             0x01FF0001
 403 #define CONFIG_SYS_CS1_CTRL             0x00000D60
 404
 405 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS0_BASE
 406 #else
 407 /* Intel Flash */
 408 #define CONFIG_SYS_CS0_BASE             0x00000000
 409 #define CONFIG_SYS_CS0_MASK             0x01FF0001
 410 #define CONFIG_SYS_CS0_CTRL             0x00000D60
 411  /* Atmel Flash */
 412 #define CONFIG_SYS_CS1_BASE             0x04000000
 413 #define CONFIG_SYS_CS1_MASK             0x00070001
 414 #define CONFIG_SYS_CS1_CTRL             0x00001140
 415
 416 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS1_BASE
 417 #endif
 418
 419 /* CPLD */
 420 #define CONFIG_SYS_CS2_BASE             0x08000000
 421 #define CONFIG_SYS_CS2_MASK             0x00070001
 422 #define CONFIG_SYS_CS2_CTRL             0x003f1140
 423
 424 /* FPGA */
 425 #define CONFIG_SYS_CS3_BASE             0x09000000
 426 #define CONFIG_SYS_CS3_MASK             0x00070001
 427 #define CONFIG_SYS_CS3_CTRL             0x00000020
 428
 429 #endif                          /* _M54455EVB_H */