1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF54455 EVB board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
20 #define CONFIG_M54455EVB /* M54455EVB board */
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
25 #define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*)
27 #undef CONFIG_WATCHDOG
29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
34 #define CONFIG_BOOTP_BOOTFILESIZE
36 /* Network configuration */
38 # define CONFIG_MII_INIT 1
39 # define CONFIG_SYS_DISCOVER_PHY
40 # define CONFIG_SYS_RX_ETH_BUFFER 8
41 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
42 # define CONFIG_HAS_ETH1
43 # define CONFIG_ETHPRIME "FEC0"
44 # define CONFIG_IPADDR 192.162.1.2
45 # define CONFIG_NETMASK 255.255.255.0
46 # define CONFIG_SERVERIP 192.162.1.1
47 # define CONFIG_GATEWAYIP 192.162.1.1
49 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
50 # ifndef CONFIG_SYS_DISCOVER_PHY
51 # define FECDUPLEX FULL
52 # define FECSPEED _100BASET
54 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
55 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57 # endif /* CONFIG_SYS_DISCOVER_PHY */
60 #define CONFIG_HOSTNAME "M54455EVB"
61 #ifdef CONFIG_SYS_STMICRO_BOOT
62 /* ST Micro serial flash */
63 #define CONFIG_SYS_LOAD_ADDR2 0x40010013
64 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
67 "loadaddr=0x40010000\0" \
68 "sbfhdr=sbfhdr.bin\0" \
69 "uboot=u-boot.bin\0" \
70 "load=tftp ${loadaddr} ${sbfhdr};" \
71 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
72 "upd=run load; run prog\0" \
73 "prog=sf probe 0:1 1000000 3;" \
75 "sf write ${loadaddr} 0 0x30000;" \
80 #ifdef CONFIG_SYS_ATMEL_BOOT
81 # define CONFIG_SYS_UBOOT_END 0x0403FFFF
82 #elif defined(CONFIG_SYS_INTEL_BOOT)
83 # define CONFIG_SYS_UBOOT_END 0x3FFFF
85 #define CONFIG_EXTRA_ENV_SETTINGS \
87 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
88 "loadaddr=0x40010000\0" \
89 "uboot=u-boot.bin\0" \
90 "load=tftp ${loadaddr} ${uboot}\0" \
91 "upd=run load; run prog\0" \
92 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
93 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
94 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
95 __stringify(CONFIG_SYS_UBOOT_END) ";" \
96 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
97 " ${filesize}; save\0" \
101 /* ATA configuration */
102 #define CONFIG_IDE_RESET 1
103 #define CONFIG_IDE_PREINIT 1
107 #define CONFIG_SYS_IDE_MAXBUS 1
108 #define CONFIG_SYS_IDE_MAXDEVICE 2
110 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
111 #define CONFIG_SYS_ATA_IDE0_OFFSET 0
113 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
114 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
115 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
116 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
119 #define CONFIG_MCFRTC
121 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
124 #define CONFIG_MCFTMR
127 #define CONFIG_SYS_I2C
128 #define CONFIG_SYS_I2C_FSL
129 #define CONFIG_SYS_FSL_I2C_SPEED 80000
130 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
131 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
132 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
134 /* DSPI and Serial Flash */
135 #define CONFIG_CF_DSPI
136 #define CONFIG_SYS_SBFHDR_SIZE 0x13
139 #ifdef CONFIG_CMD_PCI
140 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
142 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
144 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
145 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
146 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
148 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000
149 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
150 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
152 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
153 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
154 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
157 /* FPGA - Spartan 2 */
159 #define CONFIG_FPGA_COUNT 1
160 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
161 #define CONFIG_SYS_FPGA_CHECK_CTRLC
164 /* Input, PCI, Flexbus, and VCO */
165 #define CONFIG_EXTRA_CLOCK
167 #define CONFIG_PRAM 2048 /* 2048 KB */
169 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
171 #define CONFIG_SYS_MBAR 0xFC000000
174 * Low Level Configuration Settings
175 * (address mappings, register initial values, etc.)
176 * You should know what you are doing if you make changes here.
179 /*-----------------------------------------------------------------------
180 * Definitions for initial stack pointer and data area (in DPRAM)
182 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
183 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
184 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
185 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
186 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
187 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
189 /*-----------------------------------------------------------------------
190 * Start addresses for the final memory configuration
191 * (Set up by the startup code)
192 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
194 #define CONFIG_SYS_SDRAM_BASE 0x40000000
195 #define CONFIG_SYS_SDRAM_BASE1 0x48000000
196 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
197 #define CONFIG_SYS_SDRAM_CFG1 0x65311610
198 #define CONFIG_SYS_SDRAM_CFG2 0x59670000
199 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
200 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
201 #define CONFIG_SYS_SDRAM_MODE 0x00010033
202 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
205 # define CONFIG_SERIAL_BOOT
206 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
208 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
210 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
211 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
213 /* Reserve 256 kB for malloc() */
214 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
217 * For booting Linux, the board info and command line data
218 * have to be in the first 8 MB of memory, since this is
219 * the maximum mapped by the Linux kernel during initialization ??
221 /* Initial Memory map for Linux */
222 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
225 * Configuration for environment
226 * Environment is not embedded in u-boot. First time runing may have env
227 * crc error warning if there is no correct environment on the flash.
229 #undef CONFIG_ENV_OVERWRITE
231 /*-----------------------------------------------------------------------
234 #ifdef CONFIG_SYS_STMICRO_BOOT
235 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
236 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
238 #ifdef CONFIG_SYS_ATMEL_BOOT
239 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
240 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
241 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
243 #ifdef CONFIG_SYS_INTEL_BOOT
244 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
245 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
246 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
249 #ifdef CONFIG_SYS_FLASH_CFI
251 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
252 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
253 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
254 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
255 # define CONFIG_SYS_FLASH_CHECKSUM
256 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
257 # define CONFIG_FLASH_CFI_LEGACY
259 #ifdef CONFIG_FLASH_CFI_LEGACY
260 # define CONFIG_SYS_ATMEL_REGION 4
261 # define CONFIG_SYS_ATMEL_TOTALSECT 11
262 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
263 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
268 * This is setting for JFFS2 support in u-boot.
269 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
271 #ifdef CONFIG_CMD_JFFS2
272 #ifdef CF_STMICRO_BOOT
273 # define CONFIG_JFFS2_DEV "nor1"
274 # define CONFIG_JFFS2_PART_SIZE 0x01000000
275 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
277 #ifdef CONFIG_SYS_ATMEL_BOOT
278 # define CONFIG_JFFS2_DEV "nor1"
279 # define CONFIG_JFFS2_PART_SIZE 0x01000000
280 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
282 #ifdef CONFIG_SYS_INTEL_BOOT
283 # define CONFIG_JFFS2_DEV "nor0"
284 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
285 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
289 /*-----------------------------------------------------------------------
290 * Cache Configuration
292 #define CONFIG_SYS_CACHELINE_SIZE 16
294 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
295 CONFIG_SYS_INIT_RAM_SIZE - 8)
296 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
297 CONFIG_SYS_INIT_RAM_SIZE - 4)
298 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
299 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
300 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
301 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
302 CF_ACR_EN | CF_ACR_SM_ALL)
303 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
304 CF_CACR_ICINVA | CF_CACR_EUSP)
305 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
306 CF_CACR_DEC | CF_CACR_DDCM_P | \
307 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
309 /*-----------------------------------------------------------------------
310 * Memory bank definitions
313 * CS0 - NOR Flash 1, 2, 4, or 8MB
314 * CS1 - CompactFlash and registers
321 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
323 #define CONFIG_SYS_CS0_BASE 0x04000000
324 #define CONFIG_SYS_CS0_MASK 0x00070001
325 #define CONFIG_SYS_CS0_CTRL 0x00001140
327 #define CONFIG_SYS_CS1_BASE 0x00000000
328 #define CONFIG_SYS_CS1_MASK 0x01FF0001
329 #define CONFIG_SYS_CS1_CTRL 0x00000D60
331 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
334 #define CONFIG_SYS_CS0_BASE 0x00000000
335 #define CONFIG_SYS_CS0_MASK 0x01FF0001
336 #define CONFIG_SYS_CS0_CTRL 0x00000D60
338 #define CONFIG_SYS_CS1_BASE 0x04000000
339 #define CONFIG_SYS_CS1_MASK 0x00070001
340 #define CONFIG_SYS_CS1_CTRL 0x00001140
342 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
346 #define CONFIG_SYS_CS2_BASE 0x08000000
347 #define CONFIG_SYS_CS2_MASK 0x00070001
348 #define CONFIG_SYS_CS2_CTRL 0x003f1140
351 #define CONFIG_SYS_CS3_BASE 0x09000000
352 #define CONFIG_SYS_CS3_MASK 0x00070001
353 #define CONFIG_SYS_CS3_CTRL 0x00000020
355 #endif /* _M54455EVB_H */