drivers/pci/Kconfig: Add PCI
[platform/kernel/u-boot.git] / include / configs / M54455EVB.h
1 /*
2  * Configuation settings for the Freescale MCF54455 EVB board.
3  *
4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 /*
11  * board/config.h - configuration options, board specific
12  */
13
14 #ifndef _M54455EVB_H
15 #define _M54455EVB_H
16
17 /*
18  * High Level Configuration Options
19  * (easy to change)
20  */
21 #define CONFIG_M54455EVB        /* M54455EVB board */
22
23 #define CONFIG_MCFUART
24 #define CONFIG_SYS_UART_PORT            (0)
25 #define CONFIG_BAUDRATE         115200
26
27 #undef CONFIG_WATCHDOG
28
29 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
30
31 /*
32  * BOOTP options
33  */
34 #define CONFIG_BOOTP_BOOTFILESIZE
35 #define CONFIG_BOOTP_BOOTPATH
36 #define CONFIG_BOOTP_GATEWAY
37 #define CONFIG_BOOTP_HOSTNAME
38
39 /* Command line configuration */
40 #define CONFIG_CMD_DATE
41 #define CONFIG_CMD_IDE
42 #define CONFIG_CMD_JFFS2
43 #undef CONFIG_CMD_PCI
44 #define CONFIG_CMD_REGINFO
45
46 /* Network configuration */
47 #define CONFIG_MCFFEC
48 #ifdef CONFIG_MCFFEC
49 #       define CONFIG_MII               1
50 #       define CONFIG_MII_INIT          1
51 #       define CONFIG_SYS_DISCOVER_PHY
52 #       define CONFIG_SYS_RX_ETH_BUFFER 8
53 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
54
55 #       define CONFIG_SYS_FEC0_PINMUX   0
56 #       define CONFIG_SYS_FEC1_PINMUX   0
57 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
58 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC0_IOBASE
59 #       define MCFFEC_TOUT_LOOP 50000
60 #       define CONFIG_HAS_ETH1
61
62 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
63 #       define CONFIG_ETHPRIME          "FEC0"
64 #       define CONFIG_IPADDR            192.162.1.2
65 #       define CONFIG_NETMASK           255.255.255.0
66 #       define CONFIG_SERVERIP          192.162.1.1
67 #       define CONFIG_GATEWAYIP         192.162.1.1
68
69 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
70 #       ifndef CONFIG_SYS_DISCOVER_PHY
71 #               define FECDUPLEX        FULL
72 #               define FECSPEED         _100BASET
73 #       else
74 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
75 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
76 #               endif
77 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
78 #endif
79
80 #define CONFIG_HOSTNAME         M54455EVB
81 #ifdef CONFIG_SYS_STMICRO_BOOT
82 /* ST Micro serial flash */
83 #define CONFIG_SYS_LOAD_ADDR2           0x40010013
84 #define CONFIG_EXTRA_ENV_SETTINGS               \
85         "netdev=eth0\0"                         \
86         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
87         "loadaddr=0x40010000\0"                 \
88         "sbfhdr=sbfhdr.bin\0"                   \
89         "uboot=u-boot.bin\0"                    \
90         "load=tftp ${loadaddr} ${sbfhdr};"      \
91         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
92         "upd=run load; run prog\0"              \
93         "prog=sf probe 0:1 1000000 3;"          \
94         "sf erase 0 30000;"                     \
95         "sf write ${loadaddr} 0 0x30000;"       \
96         "save\0"                                \
97         ""
98 #else
99 /* Atmel and Intel */
100 #ifdef CONFIG_SYS_ATMEL_BOOT
101 #       define CONFIG_SYS_UBOOT_END     0x0403FFFF
102 #elif defined(CONFIG_SYS_INTEL_BOOT)
103 #       define CONFIG_SYS_UBOOT_END     0x3FFFF
104 #endif
105 #define CONFIG_EXTRA_ENV_SETTINGS               \
106         "netdev=eth0\0"                         \
107         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
108         "loadaddr=0x40010000\0"                 \
109         "uboot=u-boot.bin\0"                    \
110         "load=tftp ${loadaddr} ${uboot}\0"      \
111         "upd=run load; run prog\0"              \
112         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
113         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
114         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
115         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
116         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
117         " ${filesize}; save\0"                  \
118         ""
119 #endif
120
121 /* ATA configuration */
122 #define CONFIG_ISO_PARTITION
123 #define CONFIG_DOS_PARTITION
124 #define CONFIG_IDE_RESET        1
125 #define CONFIG_IDE_PREINIT      1
126 #define CONFIG_ATAPI
127 #undef CONFIG_LBA48
128
129 #define CONFIG_SYS_IDE_MAXBUS           1
130 #define CONFIG_SYS_IDE_MAXDEVICE        2
131
132 #define CONFIG_SYS_ATA_BASE_ADDR        0x90000000
133 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
134
135 #define CONFIG_SYS_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O                            */
136 #define CONFIG_SYS_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
137 #define CONFIG_SYS_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers           */
138 #define CONFIG_SYS_ATA_STRIDE           4       /* Interval between registers                 */
139
140 /* Realtime clock */
141 #define CONFIG_MCFRTC
142 #undef RTC_DEBUG
143 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
144
145 /* Timer */
146 #define CONFIG_MCFTMR
147 #undef CONFIG_MCFPIT
148
149 /* I2c */
150 #define CONFIG_SYS_I2C
151 #define CONFIG_SYS_I2C_FSL
152 #define CONFIG_SYS_FSL_I2C_SPEED        80000
153 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
154 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
155 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
156
157 /* DSPI and Serial Flash */
158 #define CONFIG_CF_SPI
159 #define CONFIG_CF_DSPI
160 #define CONFIG_HARD_SPI
161 #define CONFIG_SYS_SBFHDR_SIZE          0x13
162 #ifdef CONFIG_CMD_SPI
163
164 #       define CONFIG_SYS_DSPI_CTAR0            (DSPI_CTAR_TRSZ(7) | \
165                                          DSPI_CTAR_PCSSCK_1CLK | \
166                                          DSPI_CTAR_PASC(0) | \
167                                          DSPI_CTAR_PDT(0) | \
168                                          DSPI_CTAR_CSSCK(0) | \
169                                          DSPI_CTAR_ASC(0) | \
170                                          DSPI_CTAR_DT(1))
171 #endif
172
173 /* PCI */
174 #ifdef CONFIG_CMD_PCI
175 #define CONFIG_PCI_PNP          1
176 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
177
178 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  4
179
180 #define CONFIG_SYS_PCI_MEM_BUS          0xA0000000
181 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
182 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
183
184 #define CONFIG_SYS_PCI_IO_BUS           0xB1000000
185 #define CONFIG_SYS_PCI_IO_PHYS          CONFIG_SYS_PCI_IO_BUS
186 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000
187
188 #define CONFIG_SYS_PCI_CFG_BUS          0xB0000000
189 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
190 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
191 #endif
192
193 /* FPGA - Spartan 2 */
194 /* experiment
195 #define CONFIG_FPGA
196 #define CONFIG_FPGA_COUNT       1
197 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
198 #define CONFIG_SYS_FPGA_CHECK_CTRLC
199 */
200
201 /* Input, PCI, Flexbus, and VCO */
202 #define CONFIG_EXTRA_CLOCK
203
204 #define CONFIG_PRAM             2048    /* 2048 KB */
205
206 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
207
208 #if defined(CONFIG_CMD_KGDB)
209 #define CONFIG_SYS_CBSIZE                       1024    /* Console I/O Buffer Size */
210 #else
211 #define CONFIG_SYS_CBSIZE                       256     /* Console I/O Buffer Size */
212 #endif
213 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
214 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
215 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
216
217 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
218
219 #define CONFIG_SYS_MBAR         0xFC000000
220
221 /*
222  * Low Level Configuration Settings
223  * (address mappings, register initial values, etc.)
224  * You should know what you are doing if you make changes here.
225  */
226
227 /*-----------------------------------------------------------------------
228  * Definitions for initial stack pointer and data area (in DPRAM)
229  */
230 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
231 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
232 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
233 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
234 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
235 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
236
237 /*-----------------------------------------------------------------------
238  * Start addresses for the final memory configuration
239  * (Set up by the startup code)
240  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
241  */
242 #define CONFIG_SYS_SDRAM_BASE           0x40000000
243 #define CONFIG_SYS_SDRAM_BASE1          0x48000000
244 #define CONFIG_SYS_SDRAM_SIZE           256     /* SDRAM size in MB */
245 #define CONFIG_SYS_SDRAM_CFG1           0x65311610
246 #define CONFIG_SYS_SDRAM_CFG2           0x59670000
247 #define CONFIG_SYS_SDRAM_CTRL           0xEA0B2000
248 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
249 #define CONFIG_SYS_SDRAM_MODE           0x00010033
250 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0xAA
251
252 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
253 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
254
255 #ifdef CONFIG_CF_SBF
256 #       define CONFIG_SERIAL_BOOT
257 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
258 #else
259 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
260 #endif
261 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
262 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
263
264 /* Reserve 256 kB for malloc() */
265 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
266
267 /*
268  * For booting Linux, the board info and command line data
269  * have to be in the first 8 MB of memory, since this is
270  * the maximum mapped by the Linux kernel during initialization ??
271  */
272 /* Initial Memory map for Linux */
273 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
274
275 /*
276  * Configuration for environment
277  * Environment is not embedded in u-boot. First time runing may have env
278  * crc error warning if there is no correct environment on the flash.
279  */
280 #ifdef CONFIG_CF_SBF
281 #       define CONFIG_ENV_IS_IN_SPI_FLASH
282 #       define CONFIG_ENV_SPI_CS                1
283 #else
284 #       define CONFIG_ENV_IS_IN_FLASH   1
285 #endif
286 #undef CONFIG_ENV_OVERWRITE
287
288 /*-----------------------------------------------------------------------
289  * FLASH organization
290  */
291 #ifdef CONFIG_SYS_STMICRO_BOOT
292 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
293 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS1_BASE
294 #       define CONFIG_ENV_OFFSET                0x30000
295 #       define CONFIG_ENV_SIZE          0x2000
296 #       define CONFIG_ENV_SECT_SIZE     0x10000
297 #endif
298 #ifdef CONFIG_SYS_ATMEL_BOOT
299 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
300 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
301 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
302 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
303 #       define CONFIG_ENV_SIZE          0x2000
304 #       define CONFIG_ENV_SECT_SIZE     0x10000
305 #endif
306 #ifdef CONFIG_SYS_INTEL_BOOT
307 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
308 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
309 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
310 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
311 #       define CONFIG_ENV_SIZE          0x2000
312 #       define CONFIG_ENV_SECT_SIZE     0x20000
313 #endif
314
315 #define CONFIG_SYS_FLASH_CFI
316 #ifdef CONFIG_SYS_FLASH_CFI
317
318 #       define CONFIG_FLASH_CFI_DRIVER  1
319 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
320 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
321 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_8BIT
322 #       define CONFIG_SYS_MAX_FLASH_BANKS       2       /* max number of memory banks */
323 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
324 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
325 #       define CONFIG_SYS_FLASH_CHECKSUM
326 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
327 #       define CONFIG_FLASH_CFI_LEGACY
328
329 #ifdef CONFIG_FLASH_CFI_LEGACY
330 #       define CONFIG_SYS_ATMEL_REGION          4
331 #       define CONFIG_SYS_ATMEL_TOTALSECT       11
332 #       define CONFIG_SYS_ATMEL_SECT            {1, 2, 1, 7}
333 #       define CONFIG_SYS_ATMEL_SECTSZ          {0x4000, 0x2000, 0x8000, 0x10000}
334 #endif
335 #endif
336
337 /*
338  * This is setting for JFFS2 support in u-boot.
339  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
340  */
341 #ifdef CONFIG_CMD_JFFS2
342 #ifdef CF_STMICRO_BOOT
343 #       define CONFIG_JFFS2_DEV         "nor1"
344 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
345 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
346 #endif
347 #ifdef CONFIG_SYS_ATMEL_BOOT
348 #       define CONFIG_JFFS2_DEV         "nor1"
349 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
350 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
351 #endif
352 #ifdef CONFIG_SYS_INTEL_BOOT
353 #       define CONFIG_JFFS2_DEV         "nor0"
354 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x500000)
355 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
356 #endif
357 #endif
358
359 /*-----------------------------------------------------------------------
360  * Cache Configuration
361  */
362 #define CONFIG_SYS_CACHELINE_SIZE               16
363
364 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
365                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
366 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
367                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
368 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
369 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
370 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
371                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
372                                          CF_ACR_EN | CF_ACR_SM_ALL)
373 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
374                                          CF_CACR_ICINVA | CF_CACR_EUSP)
375 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
376                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
377                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
378
379 /*-----------------------------------------------------------------------
380  * Memory bank definitions
381  */
382 /*
383  * CS0 - NOR Flash 1, 2, 4, or 8MB
384  * CS1 - CompactFlash and registers
385  * CS2 - CPLD
386  * CS3 - FPGA
387  * CS4 - Available
388  * CS5 - Available
389  */
390
391 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
392  /* Atmel Flash */
393 #define CONFIG_SYS_CS0_BASE             0x04000000
394 #define CONFIG_SYS_CS0_MASK             0x00070001
395 #define CONFIG_SYS_CS0_CTRL             0x00001140
396 /* Intel Flash */
397 #define CONFIG_SYS_CS1_BASE             0x00000000
398 #define CONFIG_SYS_CS1_MASK             0x01FF0001
399 #define CONFIG_SYS_CS1_CTRL             0x00000D60
400
401 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS0_BASE
402 #else
403 /* Intel Flash */
404 #define CONFIG_SYS_CS0_BASE             0x00000000
405 #define CONFIG_SYS_CS0_MASK             0x01FF0001
406 #define CONFIG_SYS_CS0_CTRL             0x00000D60
407  /* Atmel Flash */
408 #define CONFIG_SYS_CS1_BASE             0x04000000
409 #define CONFIG_SYS_CS1_MASK             0x00070001
410 #define CONFIG_SYS_CS1_CTRL             0x00001140
411
412 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS1_BASE
413 #endif
414
415 /* CPLD */
416 #define CONFIG_SYS_CS2_BASE             0x08000000
417 #define CONFIG_SYS_CS2_MASK             0x00070001
418 #define CONFIG_SYS_CS2_CTRL             0x003f1140
419
420 /* FPGA */
421 #define CONFIG_SYS_CS3_BASE             0x09000000
422 #define CONFIG_SYS_CS3_MASK             0x00070001
423 #define CONFIG_SYS_CS3_CTRL             0x00000020
424
425 #endif                          /* _M54455EVB_H */