1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF54455 EVB board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
16 #include <linux/stringify.h>
19 * High Level Configuration Options
22 #define CONFIG_M54455EVB /* M54455EVB board */
24 #define CONFIG_MCFUART
25 #define CONFIG_SYS_UART_PORT (0)
27 #define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*)
29 #undef CONFIG_WATCHDOG
31 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
36 #define CONFIG_BOOTP_BOOTFILESIZE
38 /* Network configuration */
40 # define CONFIG_MII_INIT 1
41 # define CONFIG_SYS_DISCOVER_PHY
42 # define CONFIG_SYS_RX_ETH_BUFFER 8
43 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
44 # define CONFIG_HAS_ETH1
45 # define CONFIG_ETHPRIME "FEC0"
46 # define CONFIG_IPADDR 192.162.1.2
47 # define CONFIG_NETMASK 255.255.255.0
48 # define CONFIG_SERVERIP 192.162.1.1
49 # define CONFIG_GATEWAYIP 192.162.1.1
51 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
52 # ifndef CONFIG_SYS_DISCOVER_PHY
53 # define FECDUPLEX FULL
54 # define FECSPEED _100BASET
56 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
59 # endif /* CONFIG_SYS_DISCOVER_PHY */
62 #define CONFIG_HOSTNAME "M54455EVB"
63 #ifdef CONFIG_SYS_STMICRO_BOOT
64 /* ST Micro serial flash */
65 #define CONFIG_SYS_LOAD_ADDR2 0x40010013
66 #define CONFIG_EXTRA_ENV_SETTINGS \
68 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
69 "loadaddr=0x40010000\0" \
70 "sbfhdr=sbfhdr.bin\0" \
71 "uboot=u-boot.bin\0" \
72 "load=tftp ${loadaddr} ${sbfhdr};" \
73 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
74 "upd=run load; run prog\0" \
75 "prog=sf probe 0:1 1000000 3;" \
77 "sf write ${loadaddr} 0 0x30000;" \
82 #ifdef CONFIG_SYS_ATMEL_BOOT
83 # define CONFIG_SYS_UBOOT_END 0x0403FFFF
84 #elif defined(CONFIG_SYS_INTEL_BOOT)
85 # define CONFIG_SYS_UBOOT_END 0x3FFFF
87 #define CONFIG_EXTRA_ENV_SETTINGS \
89 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
90 "loadaddr=0x40010000\0" \
91 "uboot=u-boot.bin\0" \
92 "load=tftp ${loadaddr} ${uboot}\0" \
93 "upd=run load; run prog\0" \
94 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
95 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
96 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
97 __stringify(CONFIG_SYS_UBOOT_END) ";" \
98 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
99 " ${filesize}; save\0" \
103 /* ATA configuration */
104 #define CONFIG_IDE_RESET 1
105 #define CONFIG_IDE_PREINIT 1
109 #define CONFIG_SYS_IDE_MAXBUS 1
110 #define CONFIG_SYS_IDE_MAXDEVICE 2
112 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
113 #define CONFIG_SYS_ATA_IDE0_OFFSET 0
115 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
116 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
117 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
118 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
121 #define CONFIG_MCFRTC
123 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
126 #define CONFIG_MCFTMR
129 #define CONFIG_SYS_I2C
130 #define CONFIG_SYS_I2C_FSL
131 #define CONFIG_SYS_FSL_I2C_SPEED 80000
132 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
133 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
134 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
136 /* DSPI and Serial Flash */
137 #define CONFIG_CF_DSPI
138 #define CONFIG_SYS_SBFHDR_SIZE 0x13
141 #ifdef CONFIG_CMD_PCI
142 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
144 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
146 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
147 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
148 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
150 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000
151 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
152 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
154 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
155 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
156 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
159 /* FPGA - Spartan 2 */
161 #define CONFIG_FPGA_COUNT 1
162 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
163 #define CONFIG_SYS_FPGA_CHECK_CTRLC
166 /* Input, PCI, Flexbus, and VCO */
167 #define CONFIG_EXTRA_CLOCK
169 #define CONFIG_PRAM 2048 /* 2048 KB */
171 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
173 #define CONFIG_SYS_MBAR 0xFC000000
176 * Low Level Configuration Settings
177 * (address mappings, register initial values, etc.)
178 * You should know what you are doing if you make changes here.
181 /*-----------------------------------------------------------------------
182 * Definitions for initial stack pointer and data area (in DPRAM)
184 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
185 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
186 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
187 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
188 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
189 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
191 /*-----------------------------------------------------------------------
192 * Start addresses for the final memory configuration
193 * (Set up by the startup code)
194 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
196 #define CONFIG_SYS_SDRAM_BASE 0x40000000
197 #define CONFIG_SYS_SDRAM_BASE1 0x48000000
198 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
199 #define CONFIG_SYS_SDRAM_CFG1 0x65311610
200 #define CONFIG_SYS_SDRAM_CFG2 0x59670000
201 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
202 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
203 #define CONFIG_SYS_SDRAM_MODE 0x00010033
204 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
207 # define CONFIG_SERIAL_BOOT
208 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
210 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
212 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
213 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
215 /* Reserve 256 kB for malloc() */
216 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
219 * For booting Linux, the board info and command line data
220 * have to be in the first 8 MB of memory, since this is
221 * the maximum mapped by the Linux kernel during initialization ??
223 /* Initial Memory map for Linux */
224 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
227 * Configuration for environment
228 * Environment is not embedded in u-boot. First time runing may have env
229 * crc error warning if there is no correct environment on the flash.
231 #undef CONFIG_ENV_OVERWRITE
233 /*-----------------------------------------------------------------------
236 #ifdef CONFIG_SYS_STMICRO_BOOT
237 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
238 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
240 #ifdef CONFIG_SYS_ATMEL_BOOT
241 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
242 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
243 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
245 #ifdef CONFIG_SYS_INTEL_BOOT
246 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
247 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
248 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
251 #ifdef CONFIG_SYS_FLASH_CFI
253 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
254 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
255 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
256 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
257 # define CONFIG_SYS_FLASH_CHECKSUM
258 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
259 # define CONFIG_FLASH_CFI_LEGACY
261 #ifdef CONFIG_FLASH_CFI_LEGACY
262 # define CONFIG_SYS_ATMEL_REGION 4
263 # define CONFIG_SYS_ATMEL_TOTALSECT 11
264 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
265 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
270 * This is setting for JFFS2 support in u-boot.
271 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
273 #ifdef CONFIG_CMD_JFFS2
274 #ifdef CF_STMICRO_BOOT
275 # define CONFIG_JFFS2_DEV "nor1"
276 # define CONFIG_JFFS2_PART_SIZE 0x01000000
277 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
279 #ifdef CONFIG_SYS_ATMEL_BOOT
280 # define CONFIG_JFFS2_DEV "nor1"
281 # define CONFIG_JFFS2_PART_SIZE 0x01000000
282 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
284 #ifdef CONFIG_SYS_INTEL_BOOT
285 # define CONFIG_JFFS2_DEV "nor0"
286 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
287 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
291 /*-----------------------------------------------------------------------
292 * Cache Configuration
294 #define CONFIG_SYS_CACHELINE_SIZE 16
296 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
297 CONFIG_SYS_INIT_RAM_SIZE - 8)
298 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
299 CONFIG_SYS_INIT_RAM_SIZE - 4)
300 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
301 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
302 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
303 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
304 CF_ACR_EN | CF_ACR_SM_ALL)
305 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
306 CF_CACR_ICINVA | CF_CACR_EUSP)
307 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
308 CF_CACR_DEC | CF_CACR_DDCM_P | \
309 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
311 /*-----------------------------------------------------------------------
312 * Memory bank definitions
315 * CS0 - NOR Flash 1, 2, 4, or 8MB
316 * CS1 - CompactFlash and registers
323 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
325 #define CONFIG_SYS_CS0_BASE 0x04000000
326 #define CONFIG_SYS_CS0_MASK 0x00070001
327 #define CONFIG_SYS_CS0_CTRL 0x00001140
329 #define CONFIG_SYS_CS1_BASE 0x00000000
330 #define CONFIG_SYS_CS1_MASK 0x01FF0001
331 #define CONFIG_SYS_CS1_CTRL 0x00000D60
333 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
336 #define CONFIG_SYS_CS0_BASE 0x00000000
337 #define CONFIG_SYS_CS0_MASK 0x01FF0001
338 #define CONFIG_SYS_CS0_CTRL 0x00000D60
340 #define CONFIG_SYS_CS1_BASE 0x04000000
341 #define CONFIG_SYS_CS1_MASK 0x00070001
342 #define CONFIG_SYS_CS1_CTRL 0x00001140
344 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
348 #define CONFIG_SYS_CS2_BASE 0x08000000
349 #define CONFIG_SYS_CS2_MASK 0x00070001
350 #define CONFIG_SYS_CS2_CTRL 0x003f1140
353 #define CONFIG_SYS_CS3_BASE 0x09000000
354 #define CONFIG_SYS_CS3_MASK 0x00070001
355 #define CONFIG_SYS_CS3_CTRL 0x00000020
357 #endif /* _M54455EVB_H */