1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF54455 EVB board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
20 #define CONFIG_M54455EVB /* M54455EVB board */
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
25 #define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*)
27 #undef CONFIG_WATCHDOG
29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
34 #define CONFIG_BOOTP_BOOTFILESIZE
36 /* Network configuration */
40 # define CONFIG_MII_INIT 1
41 # define CONFIG_SYS_DISCOVER_PHY
42 # define CONFIG_SYS_RX_ETH_BUFFER 8
43 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
45 # define CONFIG_SYS_FEC0_PINMUX 0
46 # define CONFIG_SYS_FEC1_PINMUX 0
47 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
48 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
49 # define MCFFEC_TOUT_LOOP 50000
50 # define CONFIG_HAS_ETH1
52 # define CONFIG_ETHPRIME "FEC0"
53 # define CONFIG_IPADDR 192.162.1.2
54 # define CONFIG_NETMASK 255.255.255.0
55 # define CONFIG_SERVERIP 192.162.1.1
56 # define CONFIG_GATEWAYIP 192.162.1.1
58 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
59 # ifndef CONFIG_SYS_DISCOVER_PHY
60 # define FECDUPLEX FULL
61 # define FECSPEED _100BASET
63 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
64 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
66 # endif /* CONFIG_SYS_DISCOVER_PHY */
69 #define CONFIG_HOSTNAME "M54455EVB"
70 #ifdef CONFIG_SYS_STMICRO_BOOT
71 /* ST Micro serial flash */
72 #define CONFIG_SYS_LOAD_ADDR2 0x40010013
73 #define CONFIG_EXTRA_ENV_SETTINGS \
75 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
76 "loadaddr=0x40010000\0" \
77 "sbfhdr=sbfhdr.bin\0" \
78 "uboot=u-boot.bin\0" \
79 "load=tftp ${loadaddr} ${sbfhdr};" \
80 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
81 "upd=run load; run prog\0" \
82 "prog=sf probe 0:1 1000000 3;" \
84 "sf write ${loadaddr} 0 0x30000;" \
89 #ifdef CONFIG_SYS_ATMEL_BOOT
90 # define CONFIG_SYS_UBOOT_END 0x0403FFFF
91 #elif defined(CONFIG_SYS_INTEL_BOOT)
92 # define CONFIG_SYS_UBOOT_END 0x3FFFF
94 #define CONFIG_EXTRA_ENV_SETTINGS \
96 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
97 "loadaddr=0x40010000\0" \
98 "uboot=u-boot.bin\0" \
99 "load=tftp ${loadaddr} ${uboot}\0" \
100 "upd=run load; run prog\0" \
101 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
102 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
103 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
104 __stringify(CONFIG_SYS_UBOOT_END) ";" \
105 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
106 " ${filesize}; save\0" \
110 /* ATA configuration */
111 #define CONFIG_IDE_RESET 1
112 #define CONFIG_IDE_PREINIT 1
116 #define CONFIG_SYS_IDE_MAXBUS 1
117 #define CONFIG_SYS_IDE_MAXDEVICE 2
119 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
120 #define CONFIG_SYS_ATA_IDE0_OFFSET 0
122 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
123 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
124 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
125 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
128 #define CONFIG_MCFRTC
130 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
133 #define CONFIG_MCFTMR
137 #define CONFIG_SYS_I2C
138 #define CONFIG_SYS_I2C_FSL
139 #define CONFIG_SYS_FSL_I2C_SPEED 80000
140 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
141 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
142 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
144 /* DSPI and Serial Flash */
145 #define CONFIG_CF_DSPI
146 #define CONFIG_HARD_SPI
147 #define CONFIG_SYS_SBFHDR_SIZE 0x13
148 #ifdef CONFIG_CMD_SPI
150 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
151 DSPI_CTAR_PCSSCK_1CLK | \
152 DSPI_CTAR_PASC(0) | \
154 DSPI_CTAR_CSSCK(0) | \
160 #ifdef CONFIG_CMD_PCI
161 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
163 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
165 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
166 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
167 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
169 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000
170 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
171 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
173 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
174 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
175 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
178 /* FPGA - Spartan 2 */
180 #define CONFIG_FPGA_COUNT 1
181 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
182 #define CONFIG_SYS_FPGA_CHECK_CTRLC
185 /* Input, PCI, Flexbus, and VCO */
186 #define CONFIG_EXTRA_CLOCK
188 #define CONFIG_PRAM 2048 /* 2048 KB */
190 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
192 #define CONFIG_SYS_MBAR 0xFC000000
195 * Low Level Configuration Settings
196 * (address mappings, register initial values, etc.)
197 * You should know what you are doing if you make changes here.
200 /*-----------------------------------------------------------------------
201 * Definitions for initial stack pointer and data area (in DPRAM)
203 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
204 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
205 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
206 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
207 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
208 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
210 /*-----------------------------------------------------------------------
211 * Start addresses for the final memory configuration
212 * (Set up by the startup code)
213 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
215 #define CONFIG_SYS_SDRAM_BASE 0x40000000
216 #define CONFIG_SYS_SDRAM_BASE1 0x48000000
217 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
218 #define CONFIG_SYS_SDRAM_CFG1 0x65311610
219 #define CONFIG_SYS_SDRAM_CFG2 0x59670000
220 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
221 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
222 #define CONFIG_SYS_SDRAM_MODE 0x00010033
223 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
225 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
226 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
229 # define CONFIG_SERIAL_BOOT
230 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
232 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
234 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
235 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
237 /* Reserve 256 kB for malloc() */
238 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
241 * For booting Linux, the board info and command line data
242 * have to be in the first 8 MB of memory, since this is
243 * the maximum mapped by the Linux kernel during initialization ??
245 /* Initial Memory map for Linux */
246 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
249 * Configuration for environment
250 * Environment is not embedded in u-boot. First time runing may have env
251 * crc error warning if there is no correct environment on the flash.
254 # define CONFIG_ENV_SPI_CS 1
256 #undef CONFIG_ENV_OVERWRITE
258 /*-----------------------------------------------------------------------
261 #ifdef CONFIG_SYS_STMICRO_BOOT
262 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
263 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
264 # define CONFIG_ENV_OFFSET 0x30000
265 # define CONFIG_ENV_SIZE 0x2000
266 # define CONFIG_ENV_SECT_SIZE 0x10000
268 #ifdef CONFIG_SYS_ATMEL_BOOT
269 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
270 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
271 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
272 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
273 # define CONFIG_ENV_SIZE 0x2000
274 # define CONFIG_ENV_SECT_SIZE 0x10000
276 #ifdef CONFIG_SYS_INTEL_BOOT
277 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
278 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
279 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
280 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
281 # define CONFIG_ENV_SIZE 0x2000
282 # define CONFIG_ENV_SECT_SIZE 0x20000
285 #define CONFIG_SYS_FLASH_CFI
286 #ifdef CONFIG_SYS_FLASH_CFI
288 # define CONFIG_FLASH_CFI_DRIVER 1
289 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
290 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
291 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
292 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
293 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
294 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
295 # define CONFIG_SYS_FLASH_CHECKSUM
296 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
297 # define CONFIG_FLASH_CFI_LEGACY
299 #ifdef CONFIG_FLASH_CFI_LEGACY
300 # define CONFIG_SYS_ATMEL_REGION 4
301 # define CONFIG_SYS_ATMEL_TOTALSECT 11
302 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
303 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
308 * This is setting for JFFS2 support in u-boot.
309 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
311 #ifdef CONFIG_CMD_JFFS2
312 #ifdef CF_STMICRO_BOOT
313 # define CONFIG_JFFS2_DEV "nor1"
314 # define CONFIG_JFFS2_PART_SIZE 0x01000000
315 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
317 #ifdef CONFIG_SYS_ATMEL_BOOT
318 # define CONFIG_JFFS2_DEV "nor1"
319 # define CONFIG_JFFS2_PART_SIZE 0x01000000
320 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
322 #ifdef CONFIG_SYS_INTEL_BOOT
323 # define CONFIG_JFFS2_DEV "nor0"
324 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
325 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
329 /*-----------------------------------------------------------------------
330 * Cache Configuration
332 #define CONFIG_SYS_CACHELINE_SIZE 16
334 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
335 CONFIG_SYS_INIT_RAM_SIZE - 8)
336 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
337 CONFIG_SYS_INIT_RAM_SIZE - 4)
338 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
339 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
340 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
341 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
342 CF_ACR_EN | CF_ACR_SM_ALL)
343 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
344 CF_CACR_ICINVA | CF_CACR_EUSP)
345 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
346 CF_CACR_DEC | CF_CACR_DDCM_P | \
347 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
349 /*-----------------------------------------------------------------------
350 * Memory bank definitions
353 * CS0 - NOR Flash 1, 2, 4, or 8MB
354 * CS1 - CompactFlash and registers
361 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
363 #define CONFIG_SYS_CS0_BASE 0x04000000
364 #define CONFIG_SYS_CS0_MASK 0x00070001
365 #define CONFIG_SYS_CS0_CTRL 0x00001140
367 #define CONFIG_SYS_CS1_BASE 0x00000000
368 #define CONFIG_SYS_CS1_MASK 0x01FF0001
369 #define CONFIG_SYS_CS1_CTRL 0x00000D60
371 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
374 #define CONFIG_SYS_CS0_BASE 0x00000000
375 #define CONFIG_SYS_CS0_MASK 0x01FF0001
376 #define CONFIG_SYS_CS0_CTRL 0x00000D60
378 #define CONFIG_SYS_CS1_BASE 0x04000000
379 #define CONFIG_SYS_CS1_MASK 0x00070001
380 #define CONFIG_SYS_CS1_CTRL 0x00001140
382 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
386 #define CONFIG_SYS_CS2_BASE 0x08000000
387 #define CONFIG_SYS_CS2_MASK 0x00070001
388 #define CONFIG_SYS_CS2_CTRL 0x003f1140
391 #define CONFIG_SYS_CS3_BASE 0x09000000
392 #define CONFIG_SYS_CS3_MASK 0x00070001
393 #define CONFIG_SYS_CS3_CTRL 0x00000020
395 #endif /* _M54455EVB_H */