2 * Configuation settings for the Freescale MCF54451 EVB board.
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
21 #define CONFIG_M54451EVB /* M54451EVB board */
23 #define CONFIG_DISPLAY_BOARDINFO
25 #define CONFIG_MCFUART
26 #define CONFIG_SYS_UART_PORT (0)
27 #define CONFIG_BAUDRATE 115200
29 #undef CONFIG_WATCHDOG
31 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
36 #define CONFIG_BOOTP_BOOTFILESIZE
37 #define CONFIG_BOOTP_BOOTPATH
38 #define CONFIG_BOOTP_GATEWAY
39 #define CONFIG_BOOTP_HOSTNAME
41 /* Command line configuration */
42 #include <config_cmd_default.h>
44 #define CONFIG_CMD_BOOTD
45 #define CONFIG_CMD_CACHE
46 #define CONFIG_CMD_DATE
47 #define CONFIG_CMD_DHCP
48 #define CONFIG_CMD_ELF
49 #define CONFIG_CMD_FLASH
50 #define CONFIG_CMD_I2C
51 #undef CONFIG_CMD_JFFS2
52 #define CONFIG_CMD_MEMORY
53 #define CONFIG_CMD_MISC
54 #define CONFIG_CMD_MII
55 #define CONFIG_CMD_NFS
56 #define CONFIG_CMD_PING
57 #define CONFIG_CMD_REGINFO
58 #define CONFIG_CMD_SPI
61 #undef CONFIG_CMD_LOADB
62 #undef CONFIG_CMD_LOADS
64 /* Network configuration */
68 # define CONFIG_MII_INIT 1
69 # define CONFIG_SYS_DISCOVER_PHY
70 # define CONFIG_SYS_RX_ETH_BUFFER 8
71 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
73 # define CONFIG_SYS_FEC0_PINMUX 0
74 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
75 # define MCFFEC_TOUT_LOOP 50000
77 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
78 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
79 # define CONFIG_ETHPRIME "FEC0"
80 # define CONFIG_IPADDR 192.162.1.2
81 # define CONFIG_NETMASK 255.255.255.0
82 # define CONFIG_SERVERIP 192.162.1.1
83 # define CONFIG_GATEWAYIP 192.162.1.1
85 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
86 # ifndef CONFIG_SYS_DISCOVER_PHY
87 # define FECDUPLEX FULL
88 # define FECSPEED _100BASET
90 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
91 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
93 # endif /* CONFIG_SYS_DISCOVER_PHY */
96 #define CONFIG_HOSTNAME M54451EVB
97 #ifdef CONFIG_SYS_STMICRO_BOOT
98 /* ST Micro serial flash */
99 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
100 #define CONFIG_EXTRA_ENV_SETTINGS \
102 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
103 "loadaddr=0x40010000\0" \
104 "sbfhdr=sbfhdr.bin\0" \
105 "uboot=u-boot.bin\0" \
106 "load=tftp ${loadaddr} ${sbfhdr};" \
107 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
108 "upd=run load; run prog\0" \
109 "prog=sf probe 0:1 1000000 3;" \
110 "sf erase 0 30000;" \
111 "sf write ${loadaddr} 0 30000;" \
115 #define CONFIG_SYS_UBOOT_END 0x3FFFF
116 #define CONFIG_EXTRA_ENV_SETTINGS \
118 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
119 "loadaddr=40010000\0" \
120 "u-boot=u-boot.bin\0" \
121 "load=tftp ${loadaddr) ${u-boot}\0" \
122 "upd=run load; run prog\0" \
123 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
124 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
125 "cp.b ${loadaddr} 0 ${filesize};" \
131 #define CONFIG_MCFRTC
133 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
136 #define CONFIG_MCFTMR
140 #define CONFIG_SYS_I2C
141 #define CONFIG_SYS_I2C_FSL
142 #define CONFIG_SYS_FSL_I2C_SPEED 80000
143 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
144 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
145 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
147 /* DSPI and Serial Flash */
148 #define CONFIG_CF_SPI
149 #define CONFIG_CF_DSPI
150 #define CONFIG_SERIAL_FLASH
151 #define CONFIG_HARD_SPI
152 #define CONFIG_SYS_SBFHDR_SIZE 0x7
153 #ifdef CONFIG_CMD_SPI
154 # define CONFIG_SPI_FLASH
155 # define CONFIG_SPI_FLASH_STMICRO
157 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
158 DSPI_CTAR_PCSSCK_1CLK | \
159 DSPI_CTAR_PASC(0) | \
161 DSPI_CTAR_CSSCK(0) | \
164 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
165 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
168 /* Input, PCI, Flexbus, and VCO */
169 #define CONFIG_EXTRA_CLOCK
171 #define CONFIG_PRAM 2048 /* 2048 KB */
173 #define CONFIG_SYS_PROMPT "-> "
174 #define CONFIG_SYS_LONGHELP /* undef to save memory */
176 #if defined(CONFIG_CMD_KGDB)
177 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
179 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
181 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
182 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
183 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
185 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
187 #define CONFIG_SYS_MBAR 0xFC000000
190 * Low Level Configuration Settings
191 * (address mappings, register initial values, etc.)
192 * You should know what you are doing if you make changes here.
195 /*-----------------------------------------------------------------------
196 * Definitions for initial stack pointer and data area (in DPRAM)
198 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
199 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
200 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
201 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
202 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
203 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
205 /*-----------------------------------------------------------------------
206 * Start addresses for the final memory configuration
207 * (Set up by the startup code)
208 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
210 #define CONFIG_SYS_SDRAM_BASE 0x40000000
211 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
212 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30
213 #define CONFIG_SYS_SDRAM_CFG2 0x57670000
214 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
215 #define CONFIG_SYS_SDRAM_EMOD 0x80810000
216 #define CONFIG_SYS_SDRAM_MODE 0x008D0000
217 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
219 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
220 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
223 # define CONFIG_SERIAL_BOOT
224 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
226 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
228 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
229 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
231 /* Reserve 256 kB for malloc() */
232 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
234 * For booting Linux, the board info and command line data
235 * have to be in the first 8 MB of memory, since this is
236 * the maximum mapped by the Linux kernel during initialization ??
238 /* Initial Memory map for Linux */
239 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
241 /* Configuration for environment
242 * Environment is not embedded in u-boot. First time runing may have env
243 * crc error warning if there is no correct environment on the flash.
245 #if defined(CONFIG_SYS_STMICRO_BOOT)
246 # define CONFIG_ENV_IS_IN_SPI_FLASH 1
247 # define CONFIG_ENV_SPI_CS 1
248 # define CONFIG_ENV_OFFSET 0x20000
249 # define CONFIG_ENV_SIZE 0x2000
250 # define CONFIG_ENV_SECT_SIZE 0x10000
252 # define CONFIG_ENV_IS_IN_FLASH 1
253 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
254 # define CONFIG_ENV_SIZE 0x2000
255 # define CONFIG_ENV_SECT_SIZE 0x20000
257 #undef CONFIG_ENV_OVERWRITE
259 /* FLASH organization */
260 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
262 #define CONFIG_SYS_FLASH_CFI
263 #ifdef CONFIG_SYS_FLASH_CFI
265 # define CONFIG_FLASH_CFI_DRIVER 1
266 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
267 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
268 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
269 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
270 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
271 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
272 # define CONFIG_SYS_FLASH_CHECKSUM
273 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
278 * This is setting for JFFS2 support in u-boot.
279 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
281 #ifdef CONFIG_CMD_JFFS2
282 # define CONFIG_JFFS2_DEV "nor0"
283 # define CONFIG_JFFS2_PART_SIZE 0x01000000
284 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
287 /* Cache Configuration */
288 #define CONFIG_SYS_CACHELINE_SIZE 16
290 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
291 CONFIG_SYS_INIT_RAM_SIZE - 8)
292 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
293 CONFIG_SYS_INIT_RAM_SIZE - 4)
294 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
295 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
296 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
297 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
298 CF_ACR_EN | CF_ACR_SM_ALL)
299 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
300 CF_CACR_ICINVA | CF_CACR_EUSP)
301 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
302 CF_CACR_DEC | CF_CACR_DDCM_P | \
303 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
305 /*-----------------------------------------------------------------------
306 * Memory bank definitions
309 * CS0 - NOR Flash 16MB
318 #define CONFIG_SYS_CS0_BASE 0x00000000
319 #define CONFIG_SYS_CS0_MASK 0x00FF0001
320 #define CONFIG_SYS_CS0_CTRL 0x00004D80
322 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
324 #endif /* _M54451EVB_H */