2 * Configuation settings for the Freescale MCF54451 EVB board.
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
21 #define CONFIG_M54451EVB /* M54451EVB board */
23 #define CONFIG_DISPLAY_BOARDINFO
25 #define CONFIG_MCFUART
26 #define CONFIG_SYS_UART_PORT (0)
27 #define CONFIG_BAUDRATE 115200
29 #undef CONFIG_WATCHDOG
31 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
36 #define CONFIG_BOOTP_BOOTFILESIZE
37 #define CONFIG_BOOTP_BOOTPATH
38 #define CONFIG_BOOTP_GATEWAY
39 #define CONFIG_BOOTP_HOSTNAME
41 /* Command line configuration */
42 #define CONFIG_CMD_DATE
43 #undef CONFIG_CMD_JFFS2
44 #define CONFIG_CMD_REGINFO
46 /* Network configuration */
50 # define CONFIG_MII_INIT 1
51 # define CONFIG_SYS_DISCOVER_PHY
52 # define CONFIG_SYS_RX_ETH_BUFFER 8
53 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
55 # define CONFIG_SYS_FEC0_PINMUX 0
56 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
57 # define MCFFEC_TOUT_LOOP 50000
59 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
60 # define CONFIG_ETHPRIME "FEC0"
61 # define CONFIG_IPADDR 192.162.1.2
62 # define CONFIG_NETMASK 255.255.255.0
63 # define CONFIG_SERVERIP 192.162.1.1
64 # define CONFIG_GATEWAYIP 192.162.1.1
66 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
67 # ifndef CONFIG_SYS_DISCOVER_PHY
68 # define FECDUPLEX FULL
69 # define FECSPEED _100BASET
71 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
72 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
74 # endif /* CONFIG_SYS_DISCOVER_PHY */
77 #define CONFIG_HOSTNAME M54451EVB
78 #ifdef CONFIG_SYS_STMICRO_BOOT
79 /* ST Micro serial flash */
80 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
81 #define CONFIG_EXTRA_ENV_SETTINGS \
83 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
84 "loadaddr=0x40010000\0" \
85 "sbfhdr=sbfhdr.bin\0" \
86 "uboot=u-boot.bin\0" \
87 "load=tftp ${loadaddr} ${sbfhdr};" \
88 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
89 "upd=run load; run prog\0" \
90 "prog=sf probe 0:1 1000000 3;" \
92 "sf write ${loadaddr} 0 30000;" \
96 #define CONFIG_SYS_UBOOT_END 0x3FFFF
97 #define CONFIG_EXTRA_ENV_SETTINGS \
99 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
100 "loadaddr=40010000\0" \
101 "u-boot=u-boot.bin\0" \
102 "load=tftp ${loadaddr) ${u-boot}\0" \
103 "upd=run load; run prog\0" \
104 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
105 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
106 "cp.b ${loadaddr} 0 ${filesize};" \
112 #define CONFIG_MCFRTC
114 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
117 #define CONFIG_MCFTMR
121 #define CONFIG_SYS_I2C
122 #define CONFIG_SYS_I2C_FSL
123 #define CONFIG_SYS_FSL_I2C_SPEED 80000
124 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
125 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
126 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
128 /* DSPI and Serial Flash */
129 #define CONFIG_CF_SPI
130 #define CONFIG_CF_DSPI
131 #define CONFIG_SERIAL_FLASH
132 #define CONFIG_HARD_SPI
133 #define CONFIG_SYS_SBFHDR_SIZE 0x7
134 #ifdef CONFIG_CMD_SPI
136 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
137 DSPI_CTAR_PCSSCK_1CLK | \
138 DSPI_CTAR_PASC(0) | \
140 DSPI_CTAR_CSSCK(0) | \
143 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
144 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
147 /* Input, PCI, Flexbus, and VCO */
148 #define CONFIG_EXTRA_CLOCK
150 #define CONFIG_PRAM 2048 /* 2048 KB */
152 #define CONFIG_SYS_LONGHELP /* undef to save memory */
154 #if defined(CONFIG_CMD_KGDB)
155 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
157 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
159 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
160 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
161 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
163 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
165 #define CONFIG_SYS_MBAR 0xFC000000
168 * Low Level Configuration Settings
169 * (address mappings, register initial values, etc.)
170 * You should know what you are doing if you make changes here.
173 /*-----------------------------------------------------------------------
174 * Definitions for initial stack pointer and data area (in DPRAM)
176 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
177 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
178 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
179 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
180 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
181 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
183 /*-----------------------------------------------------------------------
184 * Start addresses for the final memory configuration
185 * (Set up by the startup code)
186 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
188 #define CONFIG_SYS_SDRAM_BASE 0x40000000
189 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
190 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30
191 #define CONFIG_SYS_SDRAM_CFG2 0x57670000
192 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
193 #define CONFIG_SYS_SDRAM_EMOD 0x80810000
194 #define CONFIG_SYS_SDRAM_MODE 0x008D0000
195 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
197 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
198 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
201 # define CONFIG_SERIAL_BOOT
202 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
204 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
206 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
207 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
209 /* Reserve 256 kB for malloc() */
210 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
212 * For booting Linux, the board info and command line data
213 * have to be in the first 8 MB of memory, since this is
214 * the maximum mapped by the Linux kernel during initialization ??
216 /* Initial Memory map for Linux */
217 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
219 /* Configuration for environment
220 * Environment is not embedded in u-boot. First time runing may have env
221 * crc error warning if there is no correct environment on the flash.
223 #if defined(CONFIG_SYS_STMICRO_BOOT)
224 # define CONFIG_ENV_IS_IN_SPI_FLASH 1
225 # define CONFIG_ENV_SPI_CS 1
226 # define CONFIG_ENV_OFFSET 0x20000
227 # define CONFIG_ENV_SIZE 0x2000
228 # define CONFIG_ENV_SECT_SIZE 0x10000
230 # define CONFIG_ENV_IS_IN_FLASH 1
231 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
232 # define CONFIG_ENV_SIZE 0x2000
233 # define CONFIG_ENV_SECT_SIZE 0x20000
235 #undef CONFIG_ENV_OVERWRITE
237 /* FLASH organization */
238 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
240 #define CONFIG_SYS_FLASH_CFI
241 #ifdef CONFIG_SYS_FLASH_CFI
243 # define CONFIG_FLASH_CFI_DRIVER 1
244 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
245 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
246 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
247 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
248 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
249 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
250 # define CONFIG_SYS_FLASH_CHECKSUM
251 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
256 * This is setting for JFFS2 support in u-boot.
257 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
259 #ifdef CONFIG_CMD_JFFS2
260 # define CONFIG_JFFS2_DEV "nor0"
261 # define CONFIG_JFFS2_PART_SIZE 0x01000000
262 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
265 /* Cache Configuration */
266 #define CONFIG_SYS_CACHELINE_SIZE 16
268 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
269 CONFIG_SYS_INIT_RAM_SIZE - 8)
270 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
271 CONFIG_SYS_INIT_RAM_SIZE - 4)
272 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
273 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
274 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
275 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
276 CF_ACR_EN | CF_ACR_SM_ALL)
277 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
278 CF_CACR_ICINVA | CF_CACR_EUSP)
279 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
280 CF_CACR_DEC | CF_CACR_DDCM_P | \
281 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
283 /*-----------------------------------------------------------------------
284 * Memory bank definitions
287 * CS0 - NOR Flash 16MB
296 #define CONFIG_SYS_CS0_BASE 0x00000000
297 #define CONFIG_SYS_CS0_MASK 0x00FF0001
298 #define CONFIG_SYS_CS0_CTRL 0x00004D80
300 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
302 #endif /* _M54451EVB_H */