include/configs/M54451EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF54451 EVB board.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54451EVB_H
  15 #define _M54451EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_MCF5445x         /* define processor family */
  22 #define CONFIG_M54451           /* define processor type */
  23 #define CONFIG_M54451EVB        /* M54451EVB board */
  24
  25 #define CONFIG_MCFUART
  26 #define CONFIG_SYS_UART_PORT            (0)
  27 #define CONFIG_BAUDRATE         115200
  28
  29 #undef CONFIG_WATCHDOG
  30
  31 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  32
  33 /*
  34  * BOOTP options
  35  */
  36 #define CONFIG_BOOTP_BOOTFILESIZE
  37 #define CONFIG_BOOTP_BOOTPATH
  38 #define CONFIG_BOOTP_GATEWAY
  39 #define CONFIG_BOOTP_HOSTNAME
  40
  41 /* Command line configuration */
  42 #include <config_cmd_default.h>
  43
  44 #define CONFIG_CMD_BOOTD
  45 #define CONFIG_CMD_CACHE
  46 #define CONFIG_CMD_DATE
  47 #define CONFIG_CMD_DHCP
  48 #define CONFIG_CMD_ELF
  49 #define CONFIG_CMD_FLASH
  50 #define CONFIG_CMD_I2C
  51 #undef CONFIG_CMD_JFFS2
  52 #define CONFIG_CMD_MEMORY
  53 #define CONFIG_CMD_MISC
  54 #define CONFIG_CMD_MII
  55 #define CONFIG_CMD_NET
  56 #define CONFIG_CMD_NFS
  57 #define CONFIG_CMD_PING
  58 #define CONFIG_CMD_REGINFO
  59 #define CONFIG_CMD_SPI
  60 #define CONFIG_CMD_SF
  61
  62 #undef CONFIG_CMD_LOADB
  63 #undef CONFIG_CMD_LOADS
  64
  65 /* Network configuration */
  66 #define CONFIG_MCFFEC
  67 #ifdef CONFIG_MCFFEC
  68 #       define CONFIG_MII               1
  69 #       define CONFIG_MII_INIT          1
  70 #       define CONFIG_SYS_DISCOVER_PHY
  71 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  72 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  73
  74 #       define CONFIG_SYS_FEC0_PINMUX   0
  75 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  76 #       define MCFFEC_TOUT_LOOP 50000
  77
  78 #       define CONFIG_BOOTDELAY 1       /* autoboot after 5 seconds */
  79 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
  80 #       define CONFIG_ETHADDR           00:e0:0c:bc:e5:60
  81 #       define CONFIG_ETHPRIME          "FEC0"
  82 #       define CONFIG_IPADDR            192.162.1.2
  83 #       define CONFIG_NETMASK           255.255.255.0
  84 #       define CONFIG_SERVERIP          192.162.1.1
  85 #       define CONFIG_GATEWAYIP         192.162.1.1
  86 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  87
  88 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  89 #       ifndef CONFIG_SYS_DISCOVER_PHY
  90 #               define FECDUPLEX        FULL
  91 #               define FECSPEED         _100BASET
  92 #       else
  93 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  94 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  95 #               endif
  96 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  97 #endif
  98
  99 #define CONFIG_HOSTNAME         M54451EVB
 100 #ifdef CONFIG_SYS_STMICRO_BOOT
 101 /* ST Micro serial flash */
 102 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
 103 #define CONFIG_EXTRA_ENV_SETTINGS               \
 104         "netdev=eth0\0"                         \
 105         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 106         "loadaddr=0x40010000\0"                 \
 107         "sbfhdr=sbfhdr.bin\0"                   \
 108         "uboot=u-boot.bin\0"                    \
 109         "load=tftp ${loadaddr} ${sbfhdr};"      \
 110         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
 111         "upd=run load; run prog\0"              \
 112         "prog=sf probe 0:1 1000000 3;"          \
 113         "sf erase 0 30000;"                     \
 114         "sf write ${loadaddr} 0 30000;"         \
 115         "save\0"                                \
 116         ""
 117 #else
 118 #define CONFIG_SYS_UBOOT_END    0x3FFFF
 119 #define CONFIG_EXTRA_ENV_SETTINGS               \
 120         "netdev=eth0\0"                         \
 121         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 122         "loadaddr=40010000\0"                   \
 123         "u-boot=u-boot.bin\0"                   \
 124         "load=tftp ${loadaddr) ${u-boot}\0"     \
 125         "upd=run load; run prog\0"              \
 126         "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END)    \
 127         "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;"       \
 128         "cp.b ${loadaddr} 0 ${filesize};"       \
 129         "save\0"                                \
 130         ""
 131 #endif
 132
 133 /* Realtime clock */
 134 #define CONFIG_MCFRTC
 135 #undef RTC_DEBUG
 136 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 137
 138 /* Timer */
 139 #define CONFIG_MCFTMR
 140 #undef CONFIG_MCFPIT
 141
 142 /* I2c */
 143 #define CONFIG_SYS_I2C
 144 #define CONFIG_SYS_I2C_FSL
 145 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 146 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 147 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 148 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 149
 150 /* DSPI and Serial Flash */
 151 #define CONFIG_CF_SPI
 152 #define CONFIG_CF_DSPI
 153 #define CONFIG_SERIAL_FLASH
 154 #define CONFIG_HARD_SPI
 155 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 156 #ifdef CONFIG_CMD_SPI
 157 #       define CONFIG_SPI_FLASH
 158 #       define CONFIG_SPI_FLASH_STMICRO
 159
 160 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 161                                          DSPI_CTAR_PCSSCK_1CLK | \
 162                                          DSPI_CTAR_PASC(0) | \
 163                                          DSPI_CTAR_PDT(0) | \
 164                                          DSPI_CTAR_CSSCK(0) | \
 165                                          DSPI_CTAR_ASC(0) | \
 166                                          DSPI_CTAR_DT(1))
 167 #       define CONFIG_SYS_DSPI_CTAR1    (CONFIG_SYS_DSPI_CTAR0)
 168 #       define CONFIG_SYS_DSPI_CTAR2    (CONFIG_SYS_DSPI_CTAR0)
 169 #endif
 170
 171 /* Input, PCI, Flexbus, and VCO */
 172 #define CONFIG_EXTRA_CLOCK
 173
 174 #define CONFIG_PRAM                     2048    /* 2048 KB */
 175
 176 #define CONFIG_SYS_PROMPT               "-> "
 177 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 178
 179 #if defined(CONFIG_CMD_KGDB)
 180 #define CONFIG_SYS_CBSIZE                       1024    /* Console I/O Buffer Size */
 181 #else
 182 #define CONFIG_SYS_CBSIZE                       256     /* Console I/O Buffer Size */
 183 #endif
 184 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 185 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 186 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 187
 188 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 189
 190 #define CONFIG_SYS_MBAR                 0xFC000000
 191
 192 /*
 193  * Low Level Configuration Settings
 194  * (address mappings, register initial values, etc.)
 195  * You should know what you are doing if you make changes here.
 196  */
 197
 198 /*-----------------------------------------------------------------------
 199  * Definitions for initial stack pointer and data area (in DPRAM)
 200  */
 201 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 202 #define CONFIG_SYS_INIT_RAM_SIZE        0x8000  /* Size of used area in internal SRAM */
 203 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 204 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 205 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 206 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 207
 208 /*-----------------------------------------------------------------------
 209  * Start addresses for the final memory configuration
 210  * (Set up by the startup code)
 211  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 212  */
 213 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 214 #define CONFIG_SYS_SDRAM_SIZE           128     /* SDRAM size in MB */
 215 #define CONFIG_SYS_SDRAM_CFG1           0x33633F30
 216 #define CONFIG_SYS_SDRAM_CFG2           0x57670000
 217 #define CONFIG_SYS_SDRAM_CTRL           0xE20D2C00
 218 #define CONFIG_SYS_SDRAM_EMOD           0x80810000
 219 #define CONFIG_SYS_SDRAM_MODE           0x008D0000
 220 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0x44
 221
 222 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 223 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 224
 225 #ifdef CONFIG_CF_SBF
 226 #       define CONFIG_SERIAL_BOOT
 227 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 228 #else
 229 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 230 #endif
 231 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 232 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 233
 234 /* Reserve 256 kB for malloc() */
 235 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 236 /*
 237  * For booting Linux, the board info and command line data
 238  * have to be in the first 8 MB of memory, since this is
 239  * the maximum mapped by the Linux kernel during initialization ??
 240  */
 241 /* Initial Memory map for Linux */
 242 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 243
 244 /* Configuration for environment
 245  * Environment is not embedded in u-boot. First time runing may have env
 246  * crc error warning if there is no correct environment on the flash.
 247  */
 248 #if defined(CONFIG_SYS_STMICRO_BOOT)
 249 #       define CONFIG_ENV_IS_IN_SPI_FLASH       1
 250 #       define CONFIG_ENV_SPI_CS                1
 251 #       define CONFIG_ENV_OFFSET                0x20000
 252 #       define CONFIG_ENV_SIZE          0x2000
 253 #       define CONFIG_ENV_SECT_SIZE     0x10000
 254 #else
 255 #       define CONFIG_ENV_IS_IN_FLASH   1
 256 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 257 #       define CONFIG_ENV_SIZE          0x2000
 258 #       define CONFIG_ENV_SECT_SIZE     0x20000
 259 #endif
 260 #undef CONFIG_ENV_OVERWRITE
 261
 262 /* FLASH organization */
 263 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 264
 265 #define CONFIG_SYS_FLASH_CFI
 266 #ifdef CONFIG_SYS_FLASH_CFI
 267
 268 #       define CONFIG_FLASH_CFI_DRIVER  1
 269 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 270 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 271 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 272 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 273 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 274 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 275 #       define CONFIG_SYS_FLASH_CHECKSUM
 276 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE }
 277
 278 #endif
 279
 280 /*
 281  * This is setting for JFFS2 support in u-boot.
 282  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 283  */
 284 #ifdef CONFIG_CMD_JFFS2
 285 #       define CONFIG_JFFS2_DEV         "nor0"
 286 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 287 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 288 #endif
 289
 290 /* Cache Configuration */
 291 #define CONFIG_SYS_CACHELINE_SIZE               16
 292
 293 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 294                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 295 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 296                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 297 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 298 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 299 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 300                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 301                                          CF_ACR_EN | CF_ACR_SM_ALL)
 302 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 303                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 304 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 305                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 306                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 307
 308 /*-----------------------------------------------------------------------
 309  * Memory bank definitions
 310  */
 311 /*
 312  * CS0 - NOR Flash 16MB
 313  * CS1 - Available
 314  * CS2 - Available
 315  * CS3 - Available
 316  * CS4 - Available
 317  * CS5 - Available
 318  */
 319
 320  /* Flash */
 321 #define CONFIG_SYS_CS0_BASE             0x00000000
 322 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 323 #define CONFIG_SYS_CS0_CTRL             0x00004D80
 324
 325 #define CONFIG_SYS_SPANSION_BASE        CONFIG_SYS_CS0_BASE
 326
 327 #endif                          /* _M54451EVB_H */