1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5373 FireEngine board.
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
16 #include <linux/stringify.h>
19 * High Level Configuration Options
23 #define CONFIG_SYS_UART_PORT (0)
25 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
27 #define CONFIG_SYS_UNIFY_CACHE
30 # define CONFIG_MII_INIT 1
31 # define CONFIG_SYS_DISCOVER_PHY
32 # define CONFIG_SYS_RX_ETH_BUFFER 8
33 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
34 # ifndef CONFIG_SYS_DISCOVER_PHY
35 # define FECDUPLEX FULL
36 # define FECSPEED _100BASET
37 # endif /* CONFIG_SYS_DISCOVER_PHY */
49 # define CONFIG_IPADDR 192.162.1.2
50 # define CONFIG_NETMASK 255.255.255.0
51 # define CONFIG_SERVERIP 192.162.1.1
52 # define CONFIG_GATEWAYIP 192.162.1.1
55 #define CONFIG_HOSTNAME "M5373EVB"
56 #define CONFIG_EXTRA_ENV_SETTINGS \
58 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
59 "u-boot=u-boot.bin\0" \
60 "load=tftp ${loadaddr) ${u-boot}\0" \
61 "upd=run load; run prog\0" \
62 "prog=prot off 0 3ffff;" \
64 "cp.b ${loadaddr} 0 ${filesize};" \
68 #define CONFIG_PRAM 512 /* 512 KB */
70 #define CONFIG_SYS_CLK 80000000
71 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
73 #define CONFIG_SYS_MBAR 0xFC000000
75 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
78 * Low Level Configuration Settings
79 * (address mappings, register initial values, etc.)
80 * You should know what you are doing if you make changes here.
82 /*-----------------------------------------------------------------------
83 * Definitions for initial stack pointer and data area (in DPRAM)
85 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
86 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
87 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
88 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
89 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
91 /*-----------------------------------------------------------------------
92 * Start addresses for the final memory configuration
93 * (Set up by the startup code)
94 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
96 #define CONFIG_SYS_SDRAM_BASE 0x40000000
97 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
98 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
99 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
100 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
101 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
102 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
104 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
105 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
107 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
110 * For booting Linux, the board info and command line data
111 * have to be in the first 8 MB of memory, since this is
112 * the maximum mapped by the Linux kernel during initialization ??
114 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
115 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
117 /*-----------------------------------------------------------------------
120 #ifdef CONFIG_SYS_FLASH_CFI
121 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
122 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
123 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
126 #ifdef CONFIG_NANDFLASH_SIZE
127 # define CONFIG_SYS_MAX_NAND_DEVICE 1
128 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
129 # define CONFIG_SYS_NAND_SIZE 1
130 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
131 # define NAND_ALLOW_ERASE_ALL 1
134 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
136 /* Configuration for environment
137 * Environment is embedded in u-boot in the second sector of the flash
140 #define LDS_BOARD_TEXT \
141 . = DEFINED(env_offset) ? env_offset : .; \
142 env/embedded.o(.text*);
144 /*-----------------------------------------------------------------------
145 * Cache Configuration
148 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
149 CONFIG_SYS_INIT_RAM_SIZE - 8)
150 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
151 CONFIG_SYS_INIT_RAM_SIZE - 4)
152 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
153 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
154 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
155 CF_ACR_EN | CF_ACR_SM_ALL)
156 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
159 /*-----------------------------------------------------------------------
160 * Chipselect bank definitions
163 * CS0 - NOR Flash 1, 2, 4, or 8MB
164 * CS1 - CompactFlash and registers
165 * CS2 - NAND Flash 16, 32, or 64MB
170 #define CONFIG_SYS_CS0_BASE 0
171 #define CONFIG_SYS_CS0_MASK 0x007f0001
172 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
174 #define CONFIG_SYS_CS1_BASE 0x10000000
175 #define CONFIG_SYS_CS1_MASK 0x001f0001
176 #define CONFIG_SYS_CS1_CTRL 0x002A3780
178 #ifdef CONFIG_NANDFLASH_SIZE
179 #define CONFIG_SYS_CS2_BASE 0x20000000
180 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
181 #define CONFIG_SYS_CS2_CTRL 0x00001f60
184 #endif /* _M5373EVB_H */