1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5373 FireEngine board.
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
16 #include <linux/stringify.h>
19 * High Level Configuration Options
23 #define CONFIG_SYS_UART_PORT (0)
25 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
27 #define CONFIG_SYS_UNIFY_CACHE
30 # define CONFIG_SYS_DISCOVER_PHY
31 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
32 # ifndef CONFIG_SYS_DISCOVER_PHY
33 # define FECDUPLEX FULL
34 # define FECSPEED _100BASET
35 # endif /* CONFIG_SYS_DISCOVER_PHY */
44 # define CONFIG_IPADDR 192.162.1.2
45 # define CONFIG_NETMASK 255.255.255.0
46 # define CONFIG_SERVERIP 192.162.1.1
47 # define CONFIG_GATEWAYIP 192.162.1.1
50 #define CONFIG_HOSTNAME "M5373EVB"
51 #define CONFIG_EXTRA_ENV_SETTINGS \
53 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
54 "u-boot=u-boot.bin\0" \
55 "load=tftp ${loadaddr) ${u-boot}\0" \
56 "upd=run load; run prog\0" \
57 "prog=prot off 0 3ffff;" \
59 "cp.b ${loadaddr} 0 ${filesize};" \
63 #define CONFIG_PRAM 512 /* 512 KB */
65 #define CONFIG_SYS_CLK 80000000
66 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
68 #define CONFIG_SYS_MBAR 0xFC000000
70 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
73 * Low Level Configuration Settings
74 * (address mappings, register initial values, etc.)
75 * You should know what you are doing if you make changes here.
77 /*-----------------------------------------------------------------------
78 * Definitions for initial stack pointer and data area (in DPRAM)
80 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
81 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
82 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
83 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
84 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
86 /*-----------------------------------------------------------------------
87 * Start addresses for the final memory configuration
88 * (Set up by the startup code)
89 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
91 #define CONFIG_SYS_SDRAM_BASE 0x40000000
92 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
93 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
94 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
95 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
96 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
97 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
99 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
100 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
102 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
105 * For booting Linux, the board info and command line data
106 * have to be in the first 8 MB of memory, since this is
107 * the maximum mapped by the Linux kernel during initialization ??
109 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
110 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
112 /*-----------------------------------------------------------------------
115 #ifdef CONFIG_SYS_FLASH_CFI
116 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
117 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
118 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
121 #ifdef CONFIG_NANDFLASH_SIZE
122 # define CONFIG_SYS_MAX_NAND_DEVICE 1
123 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
124 # define CONFIG_SYS_NAND_SIZE 1
125 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
126 # define NAND_ALLOW_ERASE_ALL 1
129 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
131 /* Configuration for environment
132 * Environment is embedded in u-boot in the second sector of the flash
135 #define LDS_BOARD_TEXT \
136 . = DEFINED(env_offset) ? env_offset : .; \
137 env/embedded.o(.text*);
139 /*-----------------------------------------------------------------------
140 * Cache Configuration
143 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
144 CONFIG_SYS_INIT_RAM_SIZE - 8)
145 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
146 CONFIG_SYS_INIT_RAM_SIZE - 4)
147 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
148 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
149 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
150 CF_ACR_EN | CF_ACR_SM_ALL)
151 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
154 /*-----------------------------------------------------------------------
155 * Chipselect bank definitions
158 * CS0 - NOR Flash 1, 2, 4, or 8MB
159 * CS1 - CompactFlash and registers
160 * CS2 - NAND Flash 16, 32, or 64MB
165 #define CONFIG_SYS_CS0_BASE 0
166 #define CONFIG_SYS_CS0_MASK 0x007f0001
167 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
169 #define CONFIG_SYS_CS1_BASE 0x10000000
170 #define CONFIG_SYS_CS1_MASK 0x001f0001
171 #define CONFIG_SYS_CS1_CTRL 0x002A3780
173 #ifdef CONFIG_NANDFLASH_SIZE
174 #define CONFIG_SYS_CS2_BASE 0x20000000
175 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
176 #define CONFIG_SYS_CS2_CTRL 0x00001f60
179 #endif /* _M5373EVB_H */