1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5373 FireEngine board.
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
16 #include <linux/stringify.h>
19 * High Level Configuration Options
23 #define CONFIG_SYS_UART_PORT (0)
25 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
27 #define CONFIG_SYS_UNIFY_CACHE
30 # define CONFIG_MII_INIT 1
31 # define CONFIG_SYS_DISCOVER_PHY
32 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
33 # ifndef CONFIG_SYS_DISCOVER_PHY
34 # define FECDUPLEX FULL
35 # define FECSPEED _100BASET
36 # endif /* CONFIG_SYS_DISCOVER_PHY */
48 # define CONFIG_IPADDR 192.162.1.2
49 # define CONFIG_NETMASK 255.255.255.0
50 # define CONFIG_SERVERIP 192.162.1.1
51 # define CONFIG_GATEWAYIP 192.162.1.1
54 #define CONFIG_HOSTNAME "M5373EVB"
55 #define CONFIG_EXTRA_ENV_SETTINGS \
57 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
58 "u-boot=u-boot.bin\0" \
59 "load=tftp ${loadaddr) ${u-boot}\0" \
60 "upd=run load; run prog\0" \
61 "prog=prot off 0 3ffff;" \
63 "cp.b ${loadaddr} 0 ${filesize};" \
67 #define CONFIG_PRAM 512 /* 512 KB */
69 #define CONFIG_SYS_CLK 80000000
70 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
72 #define CONFIG_SYS_MBAR 0xFC000000
74 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
77 * Low Level Configuration Settings
78 * (address mappings, register initial values, etc.)
79 * You should know what you are doing if you make changes here.
81 /*-----------------------------------------------------------------------
82 * Definitions for initial stack pointer and data area (in DPRAM)
84 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
85 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
86 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
87 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
88 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
90 /*-----------------------------------------------------------------------
91 * Start addresses for the final memory configuration
92 * (Set up by the startup code)
93 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
95 #define CONFIG_SYS_SDRAM_BASE 0x40000000
96 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
97 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
98 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
99 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
100 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
101 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
103 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
104 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
106 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
109 * For booting Linux, the board info and command line data
110 * have to be in the first 8 MB of memory, since this is
111 * the maximum mapped by the Linux kernel during initialization ??
113 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
114 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
116 /*-----------------------------------------------------------------------
119 #ifdef CONFIG_SYS_FLASH_CFI
120 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
121 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
122 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
125 #ifdef CONFIG_NANDFLASH_SIZE
126 # define CONFIG_SYS_MAX_NAND_DEVICE 1
127 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
128 # define CONFIG_SYS_NAND_SIZE 1
129 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
130 # define NAND_ALLOW_ERASE_ALL 1
133 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
135 /* Configuration for environment
136 * Environment is embedded in u-boot in the second sector of the flash
139 #define LDS_BOARD_TEXT \
140 . = DEFINED(env_offset) ? env_offset : .; \
141 env/embedded.o(.text*);
143 /*-----------------------------------------------------------------------
144 * Cache Configuration
147 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
148 CONFIG_SYS_INIT_RAM_SIZE - 8)
149 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
150 CONFIG_SYS_INIT_RAM_SIZE - 4)
151 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
152 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
153 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
154 CF_ACR_EN | CF_ACR_SM_ALL)
155 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
158 /*-----------------------------------------------------------------------
159 * Chipselect bank definitions
162 * CS0 - NOR Flash 1, 2, 4, or 8MB
163 * CS1 - CompactFlash and registers
164 * CS2 - NAND Flash 16, 32, or 64MB
169 #define CONFIG_SYS_CS0_BASE 0
170 #define CONFIG_SYS_CS0_MASK 0x007f0001
171 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
173 #define CONFIG_SYS_CS1_BASE 0x10000000
174 #define CONFIG_SYS_CS1_MASK 0x001f0001
175 #define CONFIG_SYS_CS1_CTRL 0x002A3780
177 #ifdef CONFIG_NANDFLASH_SIZE
178 #define CONFIG_SYS_CS2_BASE 0x20000000
179 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
180 #define CONFIG_SYS_CS2_CTRL 0x00001f60
183 #endif /* _M5373EVB_H */