1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5373 FireEngine board.
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
16 #include <linux/stringify.h>
19 * High Level Configuration Options
23 #define CONFIG_SYS_UART_PORT (0)
25 #undef CONFIG_WATCHDOG
26 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
28 #define CONFIG_SYS_UNIFY_CACHE
31 # define CONFIG_MII_INIT 1
32 # define CONFIG_SYS_DISCOVER_PHY
33 # define CONFIG_SYS_RX_ETH_BUFFER 8
34 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
35 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
36 # ifndef CONFIG_SYS_DISCOVER_PHY
37 # define FECDUPLEX FULL
38 # define FECSPEED _100BASET
40 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
41 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
43 # endif /* CONFIG_SYS_DISCOVER_PHY */
53 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
55 #define CONFIG_UDP_CHECKSUM
58 # define CONFIG_IPADDR 192.162.1.2
59 # define CONFIG_NETMASK 255.255.255.0
60 # define CONFIG_SERVERIP 192.162.1.1
61 # define CONFIG_GATEWAYIP 192.162.1.1
64 #define CONFIG_HOSTNAME "M5373EVB"
65 #define CONFIG_EXTRA_ENV_SETTINGS \
67 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
68 "u-boot=u-boot.bin\0" \
69 "load=tftp ${loadaddr) ${u-boot}\0" \
70 "upd=run load; run prog\0" \
71 "prog=prot off 0 3ffff;" \
73 "cp.b ${loadaddr} 0 ${filesize};" \
77 #define CONFIG_PRAM 512 /* 512 KB */
79 #define CONFIG_SYS_CLK 80000000
80 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
82 #define CONFIG_SYS_MBAR 0xFC000000
84 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
87 * Low Level Configuration Settings
88 * (address mappings, register initial values, etc.)
89 * You should know what you are doing if you make changes here.
91 /*-----------------------------------------------------------------------
92 * Definitions for initial stack pointer and data area (in DPRAM)
94 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
95 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
96 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
97 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
98 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
100 /*-----------------------------------------------------------------------
101 * Start addresses for the final memory configuration
102 * (Set up by the startup code)
103 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
105 #define CONFIG_SYS_SDRAM_BASE 0x40000000
106 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
107 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
108 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
109 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
110 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
111 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
113 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
114 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
116 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
119 * For booting Linux, the board info and command line data
120 * have to be in the first 8 MB of memory, since this is
121 * the maximum mapped by the Linux kernel during initialization ??
123 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
124 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
126 /*-----------------------------------------------------------------------
129 #ifdef CONFIG_SYS_FLASH_CFI
130 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
131 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
132 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
133 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
136 #ifdef CONFIG_NANDFLASH_SIZE
137 # define CONFIG_SYS_MAX_NAND_DEVICE 1
138 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
139 # define CONFIG_SYS_NAND_SIZE 1
140 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
141 # define NAND_ALLOW_ERASE_ALL 1
142 # define CONFIG_JFFS2_NAND 1
143 # define CONFIG_JFFS2_DEV "nand0"
144 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
145 # define CONFIG_JFFS2_PART_OFFSET 0x00000000
148 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
150 /* Configuration for environment
151 * Environment is embedded in u-boot in the second sector of the flash
154 #define LDS_BOARD_TEXT \
155 . = DEFINED(env_offset) ? env_offset : .; \
156 env/embedded.o(.text*);
158 /*-----------------------------------------------------------------------
159 * Cache Configuration
162 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
163 CONFIG_SYS_INIT_RAM_SIZE - 8)
164 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
165 CONFIG_SYS_INIT_RAM_SIZE - 4)
166 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
167 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
168 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
169 CF_ACR_EN | CF_ACR_SM_ALL)
170 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
173 /*-----------------------------------------------------------------------
174 * Chipselect bank definitions
177 * CS0 - NOR Flash 1, 2, 4, or 8MB
178 * CS1 - CompactFlash and registers
179 * CS2 - NAND Flash 16, 32, or 64MB
184 #define CONFIG_SYS_CS0_BASE 0
185 #define CONFIG_SYS_CS0_MASK 0x007f0001
186 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
188 #define CONFIG_SYS_CS1_BASE 0x10000000
189 #define CONFIG_SYS_CS1_MASK 0x001f0001
190 #define CONFIG_SYS_CS1_CTRL 0x002A3780
192 #ifdef CONFIG_NANDFLASH_SIZE
193 #define CONFIG_SYS_CS2_BASE 0x20000000
194 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
195 #define CONFIG_SYS_CS2_CTRL 0x00001f60
198 #endif /* _M5373EVB_H */