1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5373 FireEngine board.
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
16 #include <linux/stringify.h>
19 * High Level Configuration Options
23 #define CONFIG_SYS_UART_PORT (0)
25 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
27 #define CONFIG_SYS_UNIFY_CACHE
30 # define CONFIG_MII_INIT 1
31 # define CONFIG_SYS_DISCOVER_PHY
32 # define CONFIG_SYS_RX_ETH_BUFFER 8
33 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
34 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
35 # ifndef CONFIG_SYS_DISCOVER_PHY
36 # define FECDUPLEX FULL
37 # define FECSPEED _100BASET
39 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
40 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
42 # endif /* CONFIG_SYS_DISCOVER_PHY */
54 # define CONFIG_IPADDR 192.162.1.2
55 # define CONFIG_NETMASK 255.255.255.0
56 # define CONFIG_SERVERIP 192.162.1.1
57 # define CONFIG_GATEWAYIP 192.162.1.1
60 #define CONFIG_HOSTNAME "M5373EVB"
61 #define CONFIG_EXTRA_ENV_SETTINGS \
63 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
64 "u-boot=u-boot.bin\0" \
65 "load=tftp ${loadaddr) ${u-boot}\0" \
66 "upd=run load; run prog\0" \
67 "prog=prot off 0 3ffff;" \
69 "cp.b ${loadaddr} 0 ${filesize};" \
73 #define CONFIG_PRAM 512 /* 512 KB */
75 #define CONFIG_SYS_CLK 80000000
76 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
78 #define CONFIG_SYS_MBAR 0xFC000000
80 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
83 * Low Level Configuration Settings
84 * (address mappings, register initial values, etc.)
85 * You should know what you are doing if you make changes here.
87 /*-----------------------------------------------------------------------
88 * Definitions for initial stack pointer and data area (in DPRAM)
90 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
91 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
92 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
93 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
94 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
96 /*-----------------------------------------------------------------------
97 * Start addresses for the final memory configuration
98 * (Set up by the startup code)
99 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
101 #define CONFIG_SYS_SDRAM_BASE 0x40000000
102 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
103 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
104 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
105 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
106 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
107 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
109 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
110 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
112 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
115 * For booting Linux, the board info and command line data
116 * have to be in the first 8 MB of memory, since this is
117 * the maximum mapped by the Linux kernel during initialization ??
119 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
120 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
122 /*-----------------------------------------------------------------------
125 #ifdef CONFIG_SYS_FLASH_CFI
126 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
127 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
128 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
131 #ifdef CONFIG_NANDFLASH_SIZE
132 # define CONFIG_SYS_MAX_NAND_DEVICE 1
133 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
134 # define CONFIG_SYS_NAND_SIZE 1
135 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
136 # define NAND_ALLOW_ERASE_ALL 1
139 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
141 /* Configuration for environment
142 * Environment is embedded in u-boot in the second sector of the flash
145 #define LDS_BOARD_TEXT \
146 . = DEFINED(env_offset) ? env_offset : .; \
147 env/embedded.o(.text*);
149 /*-----------------------------------------------------------------------
150 * Cache Configuration
153 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
154 CONFIG_SYS_INIT_RAM_SIZE - 8)
155 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
156 CONFIG_SYS_INIT_RAM_SIZE - 4)
157 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
158 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
159 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
160 CF_ACR_EN | CF_ACR_SM_ALL)
161 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
164 /*-----------------------------------------------------------------------
165 * Chipselect bank definitions
168 * CS0 - NOR Flash 1, 2, 4, or 8MB
169 * CS1 - CompactFlash and registers
170 * CS2 - NAND Flash 16, 32, or 64MB
175 #define CONFIG_SYS_CS0_BASE 0
176 #define CONFIG_SYS_CS0_MASK 0x007f0001
177 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
179 #define CONFIG_SYS_CS1_BASE 0x10000000
180 #define CONFIG_SYS_CS1_MASK 0x001f0001
181 #define CONFIG_SYS_CS1_CTRL 0x002A3780
183 #ifdef CONFIG_NANDFLASH_SIZE
184 #define CONFIG_SYS_CS2_BASE 0x20000000
185 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
186 #define CONFIG_SYS_CS2_CTRL 0x00001f60
189 #endif /* _M5373EVB_H */