1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5373 FireEngine board.
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
16 #include <linux/stringify.h>
19 * High Level Configuration Options
23 #define CONFIG_SYS_UART_PORT (0)
25 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
27 #define CONFIG_SYS_UNIFY_CACHE
30 # define CONFIG_SYS_DISCOVER_PHY
31 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
32 # ifndef CONFIG_SYS_DISCOVER_PHY
33 # define FECDUPLEX FULL
34 # define FECSPEED _100BASET
35 # endif /* CONFIG_SYS_DISCOVER_PHY */
41 # define CONFIG_IPADDR 192.162.1.2
42 # define CONFIG_NETMASK 255.255.255.0
43 # define CONFIG_SERVERIP 192.162.1.1
44 # define CONFIG_GATEWAYIP 192.162.1.1
47 #define CONFIG_HOSTNAME "M5373EVB"
48 #define CONFIG_EXTRA_ENV_SETTINGS \
50 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
51 "u-boot=u-boot.bin\0" \
52 "load=tftp ${loadaddr) ${u-boot}\0" \
53 "upd=run load; run prog\0" \
54 "prog=prot off 0 3ffff;" \
56 "cp.b ${loadaddr} 0 ${filesize};" \
60 #define CONFIG_PRAM 512 /* 512 KB */
62 #define CONFIG_SYS_CLK 80000000
63 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
65 #define CONFIG_SYS_MBAR 0xFC000000
67 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
70 * Low Level Configuration Settings
71 * (address mappings, register initial values, etc.)
72 * You should know what you are doing if you make changes here.
74 /*-----------------------------------------------------------------------
75 * Definitions for initial stack pointer and data area (in DPRAM)
77 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
78 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
79 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
81 /*-----------------------------------------------------------------------
82 * Start addresses for the final memory configuration
83 * (Set up by the startup code)
84 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
86 #define CONFIG_SYS_SDRAM_BASE 0x40000000
87 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
88 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
89 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
90 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
91 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
92 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
94 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
97 * For booting Linux, the board info and command line data
98 * have to be in the first 8 MB of memory, since this is
99 * the maximum mapped by the Linux kernel during initialization ??
101 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
102 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
104 /*-----------------------------------------------------------------------
107 #ifdef CONFIG_SYS_FLASH_CFI
108 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
109 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
112 # define CONFIG_SYS_MAX_NAND_DEVICE 1
113 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
114 # define CONFIG_SYS_NAND_SIZE 1
115 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
116 # define NAND_ALLOW_ERASE_ALL 1
118 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
120 /* Configuration for environment
121 * Environment is embedded in u-boot in the second sector of the flash
124 #define LDS_BOARD_TEXT \
125 . = DEFINED(env_offset) ? env_offset : .; \
126 env/embedded.o(.text*);
128 /*-----------------------------------------------------------------------
129 * Cache Configuration
132 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
133 CONFIG_SYS_INIT_RAM_SIZE - 8)
134 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
135 CONFIG_SYS_INIT_RAM_SIZE - 4)
136 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
137 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
138 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
139 CF_ACR_EN | CF_ACR_SM_ALL)
140 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
143 /*-----------------------------------------------------------------------
144 * Chipselect bank definitions
147 * CS0 - NOR Flash 1, 2, 4, or 8MB
148 * CS1 - CompactFlash and registers
149 * CS2 - NAND Flash 16, 32, or 64MB
154 #define CONFIG_SYS_CS0_BASE 0
155 #define CONFIG_SYS_CS0_MASK 0x007f0001
156 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
158 #define CONFIG_SYS_CS1_BASE 0x10000000
159 #define CONFIG_SYS_CS1_MASK 0x001f0001
160 #define CONFIG_SYS_CS1_CTRL 0x002A3780
162 #define CONFIG_SYS_CS2_BASE 0x20000000
163 #define CONFIG_SYS_CS2_MASK (16 << 20)
164 #define CONFIG_SYS_CS2_CTRL 0x00001f60
166 #endif /* _M5373EVB_H */