1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5373 FireEngine board.
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
16 #include <linux/stringify.h>
19 * High Level Configuration Options
23 #define CONFIG_MCFUART
24 #define CONFIG_SYS_UART_PORT (0)
26 #undef CONFIG_WATCHDOG
27 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
29 #define CONFIG_SYS_UNIFY_CACHE
32 # define CONFIG_MII_INIT 1
33 # define CONFIG_SYS_DISCOVER_PHY
34 # define CONFIG_SYS_RX_ETH_BUFFER 8
35 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
36 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
37 # ifndef CONFIG_SYS_DISCOVER_PHY
38 # define FECDUPLEX FULL
39 # define FECSPEED _100BASET
41 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
42 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
44 # endif /* CONFIG_SYS_DISCOVER_PHY */
54 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
56 #define CONFIG_UDP_CHECKSUM
59 # define CONFIG_IPADDR 192.162.1.2
60 # define CONFIG_NETMASK 255.255.255.0
61 # define CONFIG_SERVERIP 192.162.1.1
62 # define CONFIG_GATEWAYIP 192.162.1.1
65 #define CONFIG_HOSTNAME "M5373EVB"
66 #define CONFIG_EXTRA_ENV_SETTINGS \
68 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
69 "u-boot=u-boot.bin\0" \
70 "load=tftp ${loadaddr) ${u-boot}\0" \
71 "upd=run load; run prog\0" \
72 "prog=prot off 0 3ffff;" \
74 "cp.b ${loadaddr} 0 ${filesize};" \
78 #define CONFIG_PRAM 512 /* 512 KB */
80 #define CONFIG_SYS_LOAD_ADDR 0x40010000
82 #define CONFIG_SYS_CLK 80000000
83 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
85 #define CONFIG_SYS_MBAR 0xFC000000
87 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
90 * Low Level Configuration Settings
91 * (address mappings, register initial values, etc.)
92 * You should know what you are doing if you make changes here.
94 /*-----------------------------------------------------------------------
95 * Definitions for initial stack pointer and data area (in DPRAM)
97 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
98 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
99 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
100 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
101 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
103 /*-----------------------------------------------------------------------
104 * Start addresses for the final memory configuration
105 * (Set up by the startup code)
106 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
108 #define CONFIG_SYS_SDRAM_BASE 0x40000000
109 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
110 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
111 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
112 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
113 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
114 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
116 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
117 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
119 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
120 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
123 * For booting Linux, the board info and command line data
124 * have to be in the first 8 MB of memory, since this is
125 * the maximum mapped by the Linux kernel during initialization ??
127 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
128 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
130 /*-----------------------------------------------------------------------
133 #ifdef CONFIG_SYS_FLASH_CFI
134 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
135 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
136 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
137 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
140 #ifdef CONFIG_NANDFLASH_SIZE
141 # define CONFIG_SYS_MAX_NAND_DEVICE 1
142 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
143 # define CONFIG_SYS_NAND_SIZE 1
144 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
145 # define NAND_ALLOW_ERASE_ALL 1
146 # define CONFIG_JFFS2_NAND 1
147 # define CONFIG_JFFS2_DEV "nand0"
148 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
149 # define CONFIG_JFFS2_PART_OFFSET 0x00000000
152 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
154 /* Configuration for environment
155 * Environment is embedded in u-boot in the second sector of the flash
158 #define LDS_BOARD_TEXT \
159 . = DEFINED(env_offset) ? env_offset : .; \
160 env/embedded.o(.text*);
162 /*-----------------------------------------------------------------------
163 * Cache Configuration
165 #define CONFIG_SYS_CACHELINE_SIZE 16
167 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
168 CONFIG_SYS_INIT_RAM_SIZE - 8)
169 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
170 CONFIG_SYS_INIT_RAM_SIZE - 4)
171 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
172 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
173 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
174 CF_ACR_EN | CF_ACR_SM_ALL)
175 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
178 /*-----------------------------------------------------------------------
179 * Chipselect bank definitions
182 * CS0 - NOR Flash 1, 2, 4, or 8MB
183 * CS1 - CompactFlash and registers
184 * CS2 - NAND Flash 16, 32, or 64MB
189 #define CONFIG_SYS_CS0_BASE 0
190 #define CONFIG_SYS_CS0_MASK 0x007f0001
191 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
193 #define CONFIG_SYS_CS1_BASE 0x10000000
194 #define CONFIG_SYS_CS1_MASK 0x001f0001
195 #define CONFIG_SYS_CS1_CTRL 0x002A3780
197 #ifdef CONFIG_NANDFLASH_SIZE
198 #define CONFIG_SYS_CS2_BASE 0x20000000
199 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
200 #define CONFIG_SYS_CS2_CTRL 0x00001f60
203 #endif /* _M5373EVB_H */