2 * Configuation settings for the Freescale MCF5373 FireEngine board.
4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
25 #undef CONFIG_WATCHDOG
26 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
28 /* Command line configuration */
29 #define CONFIG_CMD_DATE
30 #define CONFIG_CMD_REGINFO
32 #ifdef CONFIG_NANDFLASH_SIZE
33 # define CONFIG_CMD_NAND
36 #define CONFIG_SYS_UNIFY_CACHE
41 # define CONFIG_MII_INIT 1
42 # define CONFIG_SYS_DISCOVER_PHY
43 # define CONFIG_SYS_RX_ETH_BUFFER 8
44 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
46 # define CONFIG_SYS_FEC0_PINMUX 0
47 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
48 # define MCFFEC_TOUT_LOOP 50000
49 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
50 # ifndef CONFIG_SYS_DISCOVER_PHY
51 # define FECDUPLEX FULL
52 # define FECSPEED _100BASET
54 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
55 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57 # endif /* CONFIG_SYS_DISCOVER_PHY */
68 #define CONFIG_SYS_I2C
69 #define CONFIG_SYS_I2C_FSL
70 #define CONFIG_SYS_FSL_I2C_SPEED 80000
71 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
72 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
73 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
75 #define CONFIG_UDP_CHECKSUM
78 # define CONFIG_IPADDR 192.162.1.2
79 # define CONFIG_NETMASK 255.255.255.0
80 # define CONFIG_SERVERIP 192.162.1.1
81 # define CONFIG_GATEWAYIP 192.162.1.1
84 #define CONFIG_HOSTNAME M5373EVB
85 #define CONFIG_EXTRA_ENV_SETTINGS \
87 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
88 "u-boot=u-boot.bin\0" \
89 "load=tftp ${loadaddr) ${u-boot}\0" \
90 "upd=run load; run prog\0" \
91 "prog=prot off 0 3ffff;" \
93 "cp.b ${loadaddr} 0 ${filesize};" \
97 #define CONFIG_PRAM 512 /* 512 KB */
98 #define CONFIG_SYS_LONGHELP /* undef to save memory */
100 #ifdef CONFIG_CMD_KGDB
101 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
103 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
106 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
107 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
108 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
109 #define CONFIG_SYS_LOAD_ADDR 0x40010000
111 #define CONFIG_SYS_CLK 80000000
112 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
114 #define CONFIG_SYS_MBAR 0xFC000000
116 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
119 * Low Level Configuration Settings
120 * (address mappings, register initial values, etc.)
121 * You should know what you are doing if you make changes here.
123 /*-----------------------------------------------------------------------
124 * Definitions for initial stack pointer and data area (in DPRAM)
126 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
127 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
128 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
129 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
130 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
132 /*-----------------------------------------------------------------------
133 * Start addresses for the final memory configuration
134 * (Set up by the startup code)
135 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
137 #define CONFIG_SYS_SDRAM_BASE 0x40000000
138 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
139 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
140 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
141 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
142 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
143 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
145 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
146 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
148 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
149 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
151 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
152 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
155 * For booting Linux, the board info and command line data
156 * have to be in the first 8 MB of memory, since this is
157 * the maximum mapped by the Linux kernel during initialization ??
159 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
160 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
162 /*-----------------------------------------------------------------------
165 #define CONFIG_SYS_FLASH_CFI
166 #ifdef CONFIG_SYS_FLASH_CFI
167 # define CONFIG_FLASH_CFI_DRIVER 1
168 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
169 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
170 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
171 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
172 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
175 #ifdef CONFIG_NANDFLASH_SIZE
176 # define CONFIG_SYS_MAX_NAND_DEVICE 1
177 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
178 # define CONFIG_SYS_NAND_SIZE 1
179 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
180 # define NAND_ALLOW_ERASE_ALL 1
181 # define CONFIG_JFFS2_NAND 1
182 # define CONFIG_JFFS2_DEV "nand0"
183 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
184 # define CONFIG_JFFS2_PART_OFFSET 0x00000000
187 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
189 /* Configuration for environment
190 * Environment is embedded in u-boot in the second sector of the flash
192 #define CONFIG_ENV_OFFSET 0x4000
193 #define CONFIG_ENV_SECT_SIZE 0x2000
194 #define CONFIG_ENV_IS_IN_FLASH 1
196 #define LDS_BOARD_TEXT \
197 . = DEFINED(env_offset) ? env_offset : .; \
198 common/env_embedded.o (.text*);
200 /*-----------------------------------------------------------------------
201 * Cache Configuration
203 #define CONFIG_SYS_CACHELINE_SIZE 16
205 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
206 CONFIG_SYS_INIT_RAM_SIZE - 8)
207 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
208 CONFIG_SYS_INIT_RAM_SIZE - 4)
209 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
210 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
211 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
212 CF_ACR_EN | CF_ACR_SM_ALL)
213 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
216 /*-----------------------------------------------------------------------
217 * Chipselect bank definitions
220 * CS0 - NOR Flash 1, 2, 4, or 8MB
221 * CS1 - CompactFlash and registers
222 * CS2 - NAND Flash 16, 32, or 64MB
227 #define CONFIG_SYS_CS0_BASE 0
228 #define CONFIG_SYS_CS0_MASK 0x007f0001
229 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
231 #define CONFIG_SYS_CS1_BASE 0x10000000
232 #define CONFIG_SYS_CS1_MASK 0x001f0001
233 #define CONFIG_SYS_CS1_CTRL 0x002A3780
235 #ifdef CONFIG_NANDFLASH_SIZE
236 #define CONFIG_SYS_CS2_BASE 0x20000000
237 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
238 #define CONFIG_SYS_CS2_CTRL 0x00001f60
241 #endif /* _M5373EVB_H */