2 * Configuation settings for the Freescale MCF5329 FireEngine board.
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * board/config.h - configuration options, board specific
34 * High Level Configuration Options
37 #define CONFIG_MCF532x /* define processor family */
38 #define CONFIG_M5329 /* define processor type */
42 #define CONFIG_MCFUART
43 #define CFG_UART_PORT (0)
44 #define CONFIG_BAUDRATE 115200
45 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
47 #undef CONFIG_WATCHDOG
48 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
50 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
56 (CFG_CMD_LOADB | CFG_CMD_LOADS) | \
65 #define CFG_UNIFY_CACHE
69 # define CONFIG_NET_MULTI 1
71 # define CFG_DISCOVER_PHY
72 # define CFG_RX_ETH_BUFFER 8
73 # define CFG_FAULT_ECHO_LINK_DOWN
75 # define CFG_FEC0_PINMUX 0
76 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
77 # define MCFFEC_TOUT_LOOP 50000
78 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
79 # ifndef CFG_DISCOVER_PHY
80 # define FECDUPLEX FULL
81 # define FECSPEED _100BASET
83 # ifndef CFG_FAULT_ECHO_LINK_DOWN
84 # define CFG_FAULT_ECHO_LINK_DOWN
86 # endif /* CFG_DISCOVER_PHY */
97 #define CONFIG_FSL_I2C
98 #define CONFIG_HARD_I2C /* I2C with hw support */
99 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
100 #define CFG_I2C_SPEED 80000
101 #define CFG_I2C_SLAVE 0x7F
102 #define CFG_I2C_OFFSET 0x58000
103 #define CFG_IMMR CFG_MBAR
105 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
106 #include <cmd_confdefs.h>
107 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
109 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
110 # define CONFIG_IPADDR 192.162.1.2
111 # define CONFIG_NETMASK 255.255.255.0
112 # define CONFIG_SERVERIP 192.162.1.1
113 # define CONFIG_GATEWAYIP 192.162.1.1
114 # define CONFIG_OVERWRITE_ETHADDR_ONCE
115 #endif /* FEC_ENET */
117 #define CONFIG_HOSTNAME M5329EVB
118 #define CONFIG_EXTRA_ENV_SETTINGS \
120 "loadaddr=40010000\0" \
121 "u-boot=u-boot.bin\0" \
122 "load=tftp ${loadaddr) ${u-boot}\0" \
123 "upd=run load; run prog\0" \
124 "prog=prot off 0 2ffff;" \
126 "cp.b ${loadaddr} 0 ${filesize};" \
130 #define CONFIG_PRAM 512 /* 512 KB */
131 #define CFG_PROMPT "-> "
132 #define CFG_LONGHELP /* undef to save memory */
134 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
135 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
137 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
140 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
141 #define CFG_MAXARGS 16 /* max number of command args */
142 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
143 #define CFG_LOAD_ADDR 0x40010000
146 #define CFG_CLK 80000000
147 #define CFG_CPU_CLK CFG_CLK * 3
149 #define CFG_MBAR 0xFC000000
152 * Low Level Configuration Settings
153 * (address mappings, register initial values, etc.)
154 * You should know what you are doing if you make changes here.
156 /*-----------------------------------------------------------------------
157 * Definitions for initial stack pointer and data area (in DPRAM)
159 #define CFG_INIT_RAM_ADDR 0x80000000
160 #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
161 #define CFG_INIT_RAM_CTRL 0x221
162 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
163 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
164 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
166 /*-----------------------------------------------------------------------
167 * Start addresses for the final memory configuration
168 * (Set up by the startup code)
169 * Please note that CFG_SDRAM_BASE _must_ start at 0
171 #define CFG_SDRAM_BASE 0x40000000
172 #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
173 #define CFG_SDRAM_CFG1 0x53722730
174 #define CFG_SDRAM_CFG2 0x56670000
175 #define CFG_SDRAM_CTRL 0xE1092000
176 #define CFG_SDRAM_EMOD 0x40010000
177 #define CFG_SDRAM_MODE 0x018D0000
179 #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
180 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
182 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
183 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
185 #define CFG_BOOTPARAMS_LEN 64*1024
186 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
189 * For booting Linux, the board info and command line data
190 * have to be in the first 8 MB of memory, since this is
191 * the maximum mapped by the Linux kernel during initialization ??
193 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
195 /*-----------------------------------------------------------------------
198 #define CFG_FLASH_CFI
200 # define CFG_FLASH_CFI_DRIVER 1
201 # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
202 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
203 # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
204 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
205 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
208 #define CFG_FLASH_BASE 0
209 #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
211 /* Configuration for environment
212 * Environment is embedded in u-boot in the second sector of the flash
214 #define CFG_ENV_OFFSET 0x4000
215 #define CFG_ENV_SECT_SIZE 0x2000
216 #define CFG_ENV_IS_IN_FLASH 1
217 #define CFG_ENV_IS_EMBEDDED 1
219 /*-----------------------------------------------------------------------
220 * Cache Configuration
222 #define CFG_CACHELINE_SIZE 16
224 /*-----------------------------------------------------------------------
225 * Chipselect bank definitions
228 * CS0 - NOR Flash 1, 2, 4, or 8MB
229 * CS1 - CompactFlash and registers
230 * CS2 - NAND Flash 16, 32, or 64MB
235 #define CFG_CS0_BASE 0
236 #define CFG_CS0_MASK 0x007f0001
237 #define CFG_CS0_CTRL 0x00001fa0
239 #define CFG_CS1_BASE 0x1000
240 #define CFG_CS1_MASK 0x001f0001
241 #define CFG_CS1_CTRL 0x002A3780
243 #ifdef NANDFLASH_SIZE
244 #define CFG_CS2_BASE 0x00800000
245 #define CFG_CS2_MASK 0x00ff0001
246 #define CFG_CS2_CTRL 0x00001f60
249 #define CONFIG_UDP_CHECKSUM
251 #endif /* _M5329EVB_H */