1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CFG_SYS_UART_PORT (0)
25 #define CFG_EXTRA_ENV_SETTINGS \
27 "loadaddr=40010000\0" \
28 "u-boot=u-boot.bin\0" \
29 "load=tftp ${loadaddr) ${u-boot}\0" \
30 "upd=run load; run prog\0" \
31 "prog=prot off 0 3ffff;" \
33 "cp.b ${loadaddr} 0 ${filesize};" \
37 #define CFG_PRAM 512 /* 512 KB */
39 #define CFG_SYS_CLK 80000000
40 #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
42 #define CFG_SYS_MBAR 0xFC000000
44 #define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000)
47 * Low Level Configuration Settings
48 * (address mappings, register initial values, etc.)
49 * You should know what you are doing if you make changes here.
51 /*-----------------------------------------------------------------------
52 * Definitions for initial stack pointer and data area (in DPRAM)
54 #define CFG_SYS_INIT_RAM_ADDR 0x80000000
55 #define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
56 #define CFG_SYS_INIT_RAM_CTRL 0x221
58 /*-----------------------------------------------------------------------
59 * Start addresses for the final memory configuration
60 * (Set up by the startup code)
61 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
63 #define CFG_SYS_SDRAM_BASE 0x40000000
64 #define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
65 #define CFG_SYS_SDRAM_CFG1 0x53722730
66 #define CFG_SYS_SDRAM_CFG2 0x56670000
67 #define CFG_SYS_SDRAM_CTRL 0xE1092000
68 #define CFG_SYS_SDRAM_EMOD 0x40010000
69 #define CFG_SYS_SDRAM_MODE 0x018D0000
72 * For booting Linux, the board info and command line data
73 * have to be in the first 8 MB of memory, since this is
74 * the maximum mapped by the Linux kernel during initialization ??
76 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
78 /*-----------------------------------------------------------------------
81 #ifdef CONFIG_SYS_FLASH_CFI
82 # define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
85 #ifdef CONFIG_CMD_NAND
86 # define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE
87 # define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
88 # define NAND_ALLOW_ERASE_ALL 1
91 #define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
93 /* Configuration for environment
94 * Environment is embedded in u-boot in the second sector of the flash
97 #define LDS_BOARD_TEXT \
98 . = DEFINED(env_offset) ? env_offset : .; \
99 env/embedded.o(.text*);
101 /*-----------------------------------------------------------------------
102 * Cache Configuration
105 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
106 CFG_SYS_INIT_RAM_SIZE - 8)
107 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
108 CFG_SYS_INIT_RAM_SIZE - 4)
109 #define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
110 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
111 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
112 CF_ACR_EN | CF_ACR_SM_ALL)
113 #define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
116 /*-----------------------------------------------------------------------
117 * Chipselect bank definitions
120 * CS0 - NOR Flash 1, 2, 4, or 8MB
121 * CS1 - CompactFlash and registers
122 * CS2 - NAND Flash 16, 32, or 64MB
127 #define CFG_SYS_CS0_BASE 0
128 #define CFG_SYS_CS0_MASK 0x007f0001
129 #define CFG_SYS_CS0_CTRL 0x00001fa0
131 #define CFG_SYS_CS1_BASE 0x10000000
132 #define CFG_SYS_CS1_MASK 0x001f0001
133 #define CFG_SYS_CS1_CTRL 0x002A3780
135 #ifdef CONFIG_CMD_NAND
136 #define CFG_SYS_CS2_BASE 0x20000000
137 #define CFG_SYS_CS2_MASK (16 << 20)
138 #define CFG_SYS_CS2_CTRL 0x00001f60
143 #endif /* _M5329EVB_H */