1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
21 #define CONFIG_MCFUART
22 #define CONFIG_SYS_UART_PORT (0)
24 #undef CONFIG_WATCHDOG
25 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
27 #define CONFIG_SYS_UNIFY_CACHE
30 # define CONFIG_MII_INIT 1
31 # define CONFIG_SYS_DISCOVER_PHY
32 # define CONFIG_SYS_RX_ETH_BUFFER 8
33 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
34 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
35 # ifndef CONFIG_SYS_DISCOVER_PHY
36 # define FECDUPLEX FULL
37 # define FECSPEED _100BASET
39 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
40 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
42 # endif /* CONFIG_SYS_DISCOVER_PHY */
52 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
54 #define CONFIG_UDP_CHECKSUM
57 # define CONFIG_IPADDR 192.162.1.2
58 # define CONFIG_NETMASK 255.255.255.0
59 # define CONFIG_SERVERIP 192.162.1.1
60 # define CONFIG_GATEWAYIP 192.162.1.1
63 #define CONFIG_HOSTNAME "M5329EVB"
64 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "loadaddr=40010000\0" \
67 "u-boot=u-boot.bin\0" \
68 "load=tftp ${loadaddr) ${u-boot}\0" \
69 "upd=run load; run prog\0" \
70 "prog=prot off 0 3ffff;" \
72 "cp.b ${loadaddr} 0 ${filesize};" \
76 #define CONFIG_PRAM 512 /* 512 KB */
78 #define CONFIG_SYS_CLK 80000000
79 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
81 #define CONFIG_SYS_MBAR 0xFC000000
83 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
86 * Low Level Configuration Settings
87 * (address mappings, register initial values, etc.)
88 * You should know what you are doing if you make changes here.
90 /*-----------------------------------------------------------------------
91 * Definitions for initial stack pointer and data area (in DPRAM)
93 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
94 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
95 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
96 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
97 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
99 /*-----------------------------------------------------------------------
100 * Start addresses for the final memory configuration
101 * (Set up by the startup code)
102 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
104 #define CONFIG_SYS_SDRAM_BASE 0x40000000
105 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
106 #define CONFIG_SYS_SDRAM_CFG1 0x53722730
107 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
108 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
109 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
110 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
112 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
113 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
115 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
118 * For booting Linux, the board info and command line data
119 * have to be in the first 8 MB of memory, since this is
120 * the maximum mapped by the Linux kernel during initialization ??
122 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
123 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
125 /*-----------------------------------------------------------------------
128 #ifdef CONFIG_SYS_FLASH_CFI
129 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
130 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
131 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
132 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
135 #ifdef CONFIG_NANDFLASH_SIZE
136 # define CONFIG_SYS_MAX_NAND_DEVICE 1
137 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
138 # define CONFIG_SYS_NAND_SIZE 1
139 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
140 # define NAND_ALLOW_ERASE_ALL 1
141 # define CONFIG_JFFS2_NAND 1
142 # define CONFIG_JFFS2_DEV "nand0"
143 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
144 # define CONFIG_JFFS2_PART_OFFSET 0x00000000
147 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
149 /* Configuration for environment
150 * Environment is embedded in u-boot in the second sector of the flash
153 #define LDS_BOARD_TEXT \
154 . = DEFINED(env_offset) ? env_offset : .; \
155 env/embedded.o(.text*);
157 /*-----------------------------------------------------------------------
158 * Cache Configuration
161 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
162 CONFIG_SYS_INIT_RAM_SIZE - 8)
163 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
164 CONFIG_SYS_INIT_RAM_SIZE - 4)
165 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
166 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
167 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
168 CF_ACR_EN | CF_ACR_SM_ALL)
169 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
172 /*-----------------------------------------------------------------------
173 * Chipselect bank definitions
176 * CS0 - NOR Flash 1, 2, 4, or 8MB
177 * CS1 - CompactFlash and registers
178 * CS2 - NAND Flash 16, 32, or 64MB
183 #define CONFIG_SYS_CS0_BASE 0
184 #define CONFIG_SYS_CS0_MASK 0x007f0001
185 #define CONFIG_SYS_CS0_CTRL 0x00001fa0
187 #define CONFIG_SYS_CS1_BASE 0x10000000
188 #define CONFIG_SYS_CS1_MASK 0x001f0001
189 #define CONFIG_SYS_CS1_CTRL 0x002A3780
191 #ifdef CONFIG_NANDFLASH_SIZE
192 #define CONFIG_SYS_CS2_BASE 0x20000000
193 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
194 #define CONFIG_SYS_CS2_CTRL 0x00001f60
197 #endif /* _M5329EVB_H */