include/configs/M5329EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Freescale MCF5329 FireEngine board.
   4  *
   5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M5329EVB_H
  14 #define _M5329EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20
  21 #define CONFIG_SYS_UART_PORT            (0)
  22
  23 #define CONFIG_WATCHDOG_TIMEOUT 5000    /* timeout in milliseconds, max timeout is 6.71sec */
  24
  25 #define CONFIG_SYS_UNIFY_CACHE
  26
  27 #ifdef CONFIG_MCFFEC
  28 #       define CONFIG_SYS_DISCOVER_PHY
  29 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  30 #       ifndef CONFIG_SYS_DISCOVER_PHY
  31 #               define FECDUPLEX        FULL
  32 #               define FECSPEED         _100BASET
  33 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  34 #endif
  35
  36 /* I2C */
  37
  38 #ifdef CONFIG_MCFFEC
  39 #       define CONFIG_IPADDR    192.162.1.2
  40 #       define CONFIG_NETMASK   255.255.255.0
  41 #       define CONFIG_SERVERIP  192.162.1.1
  42 #       define CONFIG_GATEWAYIP 192.162.1.1
  43 #endif                          /* FEC_ENET */
  44
  45 #define CONFIG_HOSTNAME         "M5329EVB"
  46 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  47         "netdev=eth0\0"                 \
  48         "loadaddr=40010000\0"   \
  49         "u-boot=u-boot.bin\0"   \
  50         "load=tftp ${loadaddr) ${u-boot}\0"     \
  51         "upd=run load; run prog\0"      \
  52         "prog=prot off 0 3ffff;"        \
  53         "era 0 3ffff;"  \
  54         "cp.b ${loadaddr} 0 ${filesize};"       \
  55         "save\0"        \
  56         ""
  57
  58 #define CONFIG_PRAM             512     /* 512 KB */
  59
  60 #define CONFIG_SYS_CLK                  80000000
  61 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 3
  62
  63 #define CONFIG_SYS_MBAR         0xFC000000
  64
  65 #define CONFIG_SYS_LATCH_ADDR           (CONFIG_SYS_CS1_BASE + 0x80000)
  66
  67 /*
  68  * Low Level Configuration Settings
  69  * (address mappings, register initial values, etc.)
  70  * You should know what you are doing if you make changes here.
  71  */
  72 /*-----------------------------------------------------------------------
  73  * Definitions for initial stack pointer and data area (in DPRAM)
  74  */
  75 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
  76 #define CONFIG_SYS_INIT_RAM_SIZE        0x8000  /* Size of used area in internal SRAM */
  77 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
  78 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  79 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  80
  81 /*-----------------------------------------------------------------------
  82  * Start addresses for the final memory configuration
  83  * (Set up by the startup code)
  84  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  85  */
  86 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  87 #define CONFIG_SYS_SDRAM_SIZE           32      /* SDRAM size in MB */
  88 #define CONFIG_SYS_SDRAM_CFG1           0x53722730
  89 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
  90 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
  91 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
  92 #define CONFIG_SYS_SDRAM_MODE           0x018D0000
  93
  94 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
  95
  96 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
  97
  98 /*
  99  * For booting Linux, the board info and command line data
 100  * have to be in the first 8 MB of memory, since this is
 101  * the maximum mapped by the Linux kernel during initialization ??
 102  */
 103 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 104 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 105
 106 /*-----------------------------------------------------------------------
 107  * FLASH organization
 108  */
 109 #ifdef CONFIG_SYS_FLASH_CFI
 110 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 111 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 112 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 113 #endif
 114
 115 #ifdef CONFIG_CMD_NAND
 116 #       define CONFIG_SYS_MAX_NAND_DEVICE       1
 117 #       define CONFIG_SYS_NAND_BASE             CONFIG_SYS_CS2_BASE
 118 #       define CONFIG_SYS_NAND_SIZE             1
 119 #       define CONFIG_SYS_NAND_BASE_LIST        { CONFIG_SYS_NAND_BASE }
 120 #       define NAND_ALLOW_ERASE_ALL     1
 121 #endif
 122
 123 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 124
 125 /* Configuration for environment
 126  * Environment is embedded in u-boot in the second sector of the flash
 127  */
 128
 129 #define LDS_BOARD_TEXT \
 130         . = DEFINED(env_offset) ? env_offset : .; \
 131         env/embedded.o(.text*);
 132
 133 /*-----------------------------------------------------------------------
 134  * Cache Configuration
 135  */
 136
 137 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 138                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 139 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 140                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 141 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 142 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 143                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 144                                          CF_ACR_EN | CF_ACR_SM_ALL)
 145 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 146                                          CF_CACR_DCM_P)
 147
 148 /*-----------------------------------------------------------------------
 149  * Chipselect bank definitions
 150  */
 151 /*
 152  * CS0 - NOR Flash 1, 2, 4, or 8MB
 153  * CS1 - CompactFlash and registers
 154  * CS2 - NAND Flash 16, 32, or 64MB
 155  * CS3 - Available
 156  * CS4 - Available
 157  * CS5 - Available
 158  */
 159 #define CONFIG_SYS_CS0_BASE             0
 160 #define CONFIG_SYS_CS0_MASK             0x007f0001
 161 #define CONFIG_SYS_CS0_CTRL             0x00001fa0
 162
 163 #define CONFIG_SYS_CS1_BASE             0x10000000
 164 #define CONFIG_SYS_CS1_MASK             0x001f0001
 165 #define CONFIG_SYS_CS1_CTRL             0x002A3780
 166
 167 #ifdef CONFIG_CMD_NAND
 168 #define CONFIG_SYS_CS2_BASE             0x20000000
 169 #define CONFIG_SYS_CS2_MASK             (16 << 20)
 170 #define CONFIG_SYS_CS2_CTRL             0x00001f60
 171 #endif
 172
 173 #endif                          /* _M5329EVB_H */